1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_MT7988_H 9 #define _DT_BINDINGS_CLK_MT7988_H 10 11 /* APMIXEDSYS */ 12 13 #define CLK_APMIXED_NETSYSPLL 14 #define CLK_APMIXED_MPLL 15 #define CLK_APMIXED_MMPLL 16 #define CLK_APMIXED_APLL2 17 #define CLK_APMIXED_NET1PLL 18 #define CLK_APMIXED_NET2PLL 19 #define CLK_APMIXED_WEDMCUPLL 20 #define CLK_APMIXED_SGMPLL 21 #define CLK_APMIXED_ARM_B 22 #define CLK_APMIXED_CCIPLL2_B 23 #define CLK_APMIXED_USXGMIIPLL 24 #define CLK_APMIXED_MSDCPLL 25 26 /* TOPCKGEN */ 27 28 #define CLK_TOP_XTAL 29 #define CLK_TOP_XTAL_D2 30 #define CLK_TOP_RTC_32K 31 #define CLK_TOP_RTC_32P7K 32 #define CLK_TOP_MPLL_D2 33 #define CLK_TOP_MPLL_D3_D2 34 #define CLK_TOP_MPLL_D4 35 #define CLK_TOP_MPLL_D8 36 #define CLK_TOP_MPLL_D8_D2 37 #define CLK_TOP_MMPLL_D2 38 #define CLK_TOP_MMPLL_D3_D5 39 #define CLK_TOP_MMPLL_D4 40 #define CLK_TOP_MMPLL_D6_D2 41 #define CLK_TOP_MMPLL_D8 42 #define CLK_TOP_APLL2_D4 43 #define CLK_TOP_NET1PLL_D4 44 #define CLK_TOP_NET1PLL_D5 45 #define CLK_TOP_NET1PLL_D5_D2 46 #define CLK_TOP_NET1PLL_D5_D4 47 #define CLK_TOP_NET1PLL_D8 48 #define CLK_TOP_NET1PLL_D8_D2 49 #define CLK_TOP_NET1PLL_D8_D4 50 #define CLK_TOP_NET1PLL_D8_D8 51 #define CLK_TOP_NET1PLL_D8_D16 52 #define CLK_TOP_NET2PLL_D2 53 #define CLK_TOP_NET2PLL_D4 54 #define CLK_TOP_NET2PLL_D4_D4 55 #define CLK_TOP_NET2PLL_D4_D8 56 #define CLK_TOP_NET2PLL_D6 57 #define CLK_TOP_NET2PLL_D8 58 #define CLK_TOP_NETSYS_SEL 59 #define CLK_TOP_NETSYS_500M_SEL 60 #define CLK_TOP_NETSYS_2X_SEL 61 #define CLK_TOP_NETSYS_GSW_SEL 62 #define CLK_TOP_ETH_GMII_SEL 63 #define CLK_TOP_NETSYS_MCU_SEL 64 #define CLK_TOP_NETSYS_PAO_2X_SEL 65 #define CLK_TOP_EIP197_SEL 66 #define CLK_TOP_AXI_INFRA_SEL 67 #define CLK_TOP_UART_SEL 68 #define CLK_TOP_EMMC_250M_SEL 69 #define CLK_TOP_EMMC_400M_SEL 70 #define CLK_TOP_SPI_SEL 71 #define CLK_TOP_SPIM_MST_SEL 72 #define CLK_TOP_NFI1X_SEL 73 #define CLK_TOP_SPINFI_SEL 74 #define CLK_TOP_PWM_SEL 75 #define CLK_TOP_I2C_SEL 76 #define CLK_TOP_PCIE_MBIST_250M_SEL 77 #define CLK_TOP_PEXTP_TL_SEL 78 #define CLK_TOP_PEXTP_TL_P1_SEL 79 #define CLK_TOP_PEXTP_TL_P2_SEL 80 #define CLK_TOP_PEXTP_TL_P3_SEL 81 #define CLK_TOP_USB_SYS_SEL 82 #define CLK_TOP_USB_SYS_P1_SEL 83 #define CLK_TOP_USB_XHCI_SEL 84 #define CLK_TOP_USB_XHCI_P1_SEL 85 #define CLK_TOP_USB_FRMCNT_SEL 86 #define CLK_TOP_USB_FRMCNT_P1_SEL 87 #define CLK_TOP_AUD_SEL 88 #define CLK_TOP_A1SYS_SEL 89 #define CLK_TOP_AUD_L_SEL 90 #define CLK_TOP_A_TUNER_SEL 91 #define CLK_TOP_SSPXTP_SEL 92 #define CLK_TOP_USB_PHY_SEL 93 #define CLK_TOP_USXGMII_SBUS_0_SEL 94 #define CLK_TOP_USXGMII_SBUS_1_SEL 95 #define CLK_TOP_SGM_0_SEL 96 #define CLK_TOP_SGM_SBUS_0_SEL 97 #define CLK_TOP_SGM_1_SEL 98 #define CLK_TOP_SGM_SBUS_1_SEL 99 #define CLK_TOP_XFI_PHY_0_XTAL_SEL 100 #define CLK_TOP_XFI_PHY_1_XTAL_SEL 101 #define CLK_TOP_SYSAXI_SEL 102 #define CLK_TOP_SYSAPB_SEL 103 #define CLK_TOP_ETH_REFCK_50M_SEL 104 #define CLK_TOP_ETH_SYS_200M_SEL 105 #define CLK_TOP_ETH_SYS_SEL 106 #define CLK_TOP_ETH_XGMII_SEL 107 #define CLK_TOP_BUS_TOPS_SEL 108 #define CLK_TOP_NPU_TOPS_SEL 109 #define CLK_TOP_DRAMC_SEL 110 #define CLK_TOP_DRAMC_MD32_SEL 111 #define CLK_TOP_INFRA_F26M_SEL 112 #define CLK_TOP_PEXTP_P0_SEL 113 #define CLK_TOP_PEXTP_P1_SEL 114 #define CLK_TOP_PEXTP_P2_SEL 115 #define CLK_TOP_PEXTP_P3_SEL 116 #define CLK_TOP_DA_XTP_GLB_P0_SEL 117 #define CLK_TOP_DA_XTP_GLB_P1_SEL 118 #define CLK_TOP_DA_XTP_GLB_P2_SEL 119 #define CLK_TOP_DA_XTP_GLB_P3_SEL 120 #define CLK_TOP_CKM_SEL 121 #define CLK_TOP_DA_SEL 122 #define CLK_TOP_PEXTP_SEL 123 #define CLK_TOP_TOPS_P2_26M_SEL 124 #define CLK_TOP_MCUSYS_BACKUP_625M_SEL 125 #define CLK_TOP_NETSYS_SYNC_250M_SEL 126 #define CLK_TOP_MACSEC_SEL 127 #define CLK_TOP_NETSYS_TOPS_400M_SEL 128 #define CLK_TOP_NETSYS_PPEFB_250M_SEL 129 #define CLK_TOP_NETSYS_WARP_SEL 130 #define CLK_TOP_ETH_MII_SEL 131 #define CLK_TOP_NPU_SEL 132 #define CLK_TOP_AUD_I2S_M 133 134 /* MCUSYS */ 135 136 #define CLK_MCU_BUS_DIV_SEL 137 #define CLK_MCU_ARM_DIV_SEL 138 139 /* INFRACFG_AO */ 140 141 #define CLK_INFRA_MUX_UART0_SEL 142 #define CLK_INFRA_MUX_UART1_SEL 143 #define CLK_INFRA_MUX_UART2_SEL 144 #define CLK_INFRA_MUX_SPI0_SEL 145 #define CLK_INFRA_MUX_SPI1_SEL 146 #define CLK_INFRA_MUX_SPI2_SEL 147 #define CLK_INFRA_PWM_SEL 148 #define CLK_INFRA_PWM_CK1_SEL 149 #define CLK_INFRA_PWM_CK2_SEL 150 #define CLK_INFRA_PWM_CK3_SEL 151 #define CLK_INFRA_PWM_CK4_SEL 152 #define CLK_INFRA_PWM_CK5_SEL 153 #define CLK_INFRA_PWM_CK6_SEL 154 #define CLK_INFRA_PWM_CK7_SEL 155 #define CLK_INFRA_PWM_CK8_SEL 156 #define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 157 #define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 158 #define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 159 #define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 160 161 /* INFRACFG */ 162 163 #define CLK_INFRA_PCIE_PERI_26M_CK_P0 164 #define CLK_INFRA_PCIE_PERI_26M_CK_P1 165 #define CLK_INFRA_PCIE_PERI_26M_CK_P2 166 #define CLK_INFRA_PCIE_PERI_26M_CK_P3 167 #define CLK_INFRA_66M_GPT_BCK 168 #define CLK_INFRA_66M_PWM_HCK 169 #define CLK_INFRA_66M_PWM_BCK 170 #define CLK_INFRA_66M_PWM_CK1 171 #define CLK_INFRA_66M_PWM_CK2 172 #define CLK_INFRA_66M_PWM_CK3 173 #define CLK_INFRA_66M_PWM_CK4 174 #define CLK_INFRA_66M_PWM_CK5 175 #define CLK_INFRA_66M_PWM_CK6 176 #define CLK_INFRA_66M_PWM_CK7 177 #define CLK_INFRA_66M_PWM_CK8 178 #define CLK_INFRA_133M_CQDMA_BCK 179 #define CLK_INFRA_66M_AUD_SLV_BCK 180 #define CLK_INFRA_AUD_26M 181 #define CLK_INFRA_AUD_L 182 #define CLK_INFRA_AUD_AUD 183 #define CLK_INFRA_AUD_EG2 184 #define CLK_INFRA_DRAMC_F26M 185 #define CLK_INFRA_133M_DBG_ACKM 186 #define CLK_INFRA_66M_AP_DMA_BCK 187 #define CLK_INFRA_66M_SEJ_BCK 188 #define CLK_INFRA_PRE_CK_SEJ_F13M 189 #define CLK_INFRA_26M_THERM_SYSTEM 190 #define CLK_INFRA_I2C_BCK 191 #define CLK_INFRA_52M_UART0_CK 192 #define CLK_INFRA_52M_UART1_CK 193 #define CLK_INFRA_52M_UART2_CK 194 #define CLK_INFRA_NFI 195 #define CLK_INFRA_SPINFI 196 #define CLK_INFRA_66M_NFI_HCK 197 #define CLK_INFRA_104M_SPI0 198 #define CLK_INFRA_104M_SPI1 199 #define CLK_INFRA_104M_SPI2_BCK 200 #define CLK_INFRA_66M_SPI0_HCK 201 #define CLK_INFRA_66M_SPI1_HCK 202 #define CLK_INFRA_66M_SPI2_HCK 203 #define CLK_INFRA_66M_FLASHIF_AXI 204 #define CLK_INFRA_RTC 205 #define CLK_INFRA_26M_ADC_BCK 206 #define CLK_INFRA_RC_ADC 207 #define CLK_INFRA_MSDC400 208 #define CLK_INFRA_MSDC2_HCK 209 #define CLK_INFRA_133M_MSDC_0_HCK 210 #define CLK_INFRA_66M_MSDC_0_HCK 211 #define CLK_INFRA_133M_CPUM_BCK 212 #define CLK_INFRA_BIST2FPC 213 #define CLK_INFRA_I2C_X16W_MCK_CK_P1 214 #define CLK_INFRA_I2C_X16W_PCK_CK_P1 215 #define CLK_INFRA_133M_USB_HCK 216 #define CLK_INFRA_133M_USB_HCK_CK_P1 217 #define CLK_INFRA_66M_USB_HCK 218 #define CLK_INFRA_66M_USB_HCK_CK_P1 219 #define CLK_INFRA_USB_SYS 220 #define CLK_INFRA_USB_SYS_CK_P1 221 #define CLK_INFRA_USB_REF 222 #define CLK_INFRA_USB_CK_P1 223 #define CLK_INFRA_USB_FRMCNT 224 #define CLK_INFRA_USB_FRMCNT_CK_P1 225 #define CLK_INFRA_USB_PIPE 226 #define CLK_INFRA_USB_PIPE_CK_P1 227 #define CLK_INFRA_USB_UTMI 228 #define CLK_INFRA_USB_UTMI_CK_P1 229 #define CLK_INFRA_USB_XHCI 230 #define CLK_INFRA_USB_XHCI_CK_P1 231 #define CLK_INFRA_PCIE_GFMUX_TL_P0 232 #define CLK_INFRA_PCIE_GFMUX_TL_P1 233 #define CLK_INFRA_PCIE_GFMUX_TL_P2 234 #define CLK_INFRA_PCIE_GFMUX_TL_P3 235 #define CLK_INFRA_PCIE_PIPE_P0 236 #define CLK_INFRA_PCIE_PIPE_P1 237 #define CLK_INFRA_PCIE_PIPE_P2 238 #define CLK_INFRA_PCIE_PIPE_P3 239 #define CLK_INFRA_133M_PCIE_CK_P0 240 #define CLK_INFRA_133M_PCIE_CK_P1 241 #define CLK_INFRA_133M_PCIE_CK_P2 242 #define CLK_INFRA_133M_PCIE_CK_P3 243 244 /* ETHDMA */ 245 246 #define CLK_ETHDMA_XGP1_EN 247 #define CLK_ETHDMA_XGP2_EN 248 #define CLK_ETHDMA_XGP3_EN 249 #define CLK_ETHDMA_FE_EN 250 #define CLK_ETHDMA_GP2_EN 251 #define CLK_ETHDMA_GP1_EN 252 #define CLK_ETHDMA_GP3_EN 253 #define CLK_ETHDMA_ESW_EN 254 #define CLK_ETHDMA_CRYPT0_EN 255 #define CLK_ETHDMA_NR_CLK 256 257 /* SGMIISYS_0 */ 258 259 #define CLK_SGM0_TX_EN 260 #define CLK_SGM0_RX_EN 261 #define CLK_SGMII0_NR_CLK 262 263 /* SGMIISYS_1 */ 264 265 #define CLK_SGM1_TX_EN 266 #define CLK_SGM1_RX_EN 267 #define CLK_SGMII1_NR_CLK 268 269 /* ETHWARP */ 270 271 #define CLK_ETHWARP_WOCPU2_EN 272 #define CLK_ETHWARP_WOCPU1_EN 273 #define CLK_ETHWARP_WOCPU0_EN 274 #define CLK_ETHWARP_NR_CLK 275 276 /* XFIPLL */ 277 #define CLK_XFIPLL_PLL 278 #define CLK_XFIPLL_PLL_EN 279 280 #endif /* _DT_BINDINGS_CLK_MT7988_H */ 281
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.