1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Shunli Wang <shunli.wang@mediatek.c 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_MT2701_H 8 #define _DT_BINDINGS_CLK_MT2701_H 9 10 /* TOPCKGEN */ 11 #define CLK_TOP_SYSPLL 12 #define CLK_TOP_SYSPLL_D2 13 #define CLK_TOP_SYSPLL_D3 14 #define CLK_TOP_SYSPLL_D5 15 #define CLK_TOP_SYSPLL_D7 16 #define CLK_TOP_SYSPLL1_D2 17 #define CLK_TOP_SYSPLL1_D4 18 #define CLK_TOP_SYSPLL1_D8 19 #define CLK_TOP_SYSPLL1_D16 20 #define CLK_TOP_SYSPLL2_D2 21 #define CLK_TOP_SYSPLL2_D4 22 #define CLK_TOP_SYSPLL2_D8 23 #define CLK_TOP_SYSPLL3_D2 24 #define CLK_TOP_SYSPLL3_D4 25 #define CLK_TOP_SYSPLL4_D2 26 #define CLK_TOP_SYSPLL4_D4 27 #define CLK_TOP_UNIVPLL 28 #define CLK_TOP_UNIVPLL_D2 29 #define CLK_TOP_UNIVPLL_D3 30 #define CLK_TOP_UNIVPLL_D5 31 #define CLK_TOP_UNIVPLL_D7 32 #define CLK_TOP_UNIVPLL_D26 33 #define CLK_TOP_UNIVPLL_D52 34 #define CLK_TOP_UNIVPLL_D108 35 #define CLK_TOP_USB_PHY48M 36 #define CLK_TOP_UNIVPLL1_D2 37 #define CLK_TOP_UNIVPLL1_D4 38 #define CLK_TOP_UNIVPLL1_D8 39 #define CLK_TOP_UNIVPLL2_D2 40 #define CLK_TOP_UNIVPLL2_D4 41 #define CLK_TOP_UNIVPLL2_D8 42 #define CLK_TOP_UNIVPLL2_D16 43 #define CLK_TOP_UNIVPLL2_D32 44 #define CLK_TOP_UNIVPLL3_D2 45 #define CLK_TOP_UNIVPLL3_D4 46 #define CLK_TOP_UNIVPLL3_D8 47 #define CLK_TOP_MSDCPLL 48 #define CLK_TOP_MSDCPLL_D2 49 #define CLK_TOP_MSDCPLL_D4 50 #define CLK_TOP_MSDCPLL_D8 51 #define CLK_TOP_MMPLL 52 #define CLK_TOP_MMPLL_D2 53 #define CLK_TOP_DMPLL 54 #define CLK_TOP_DMPLL_D2 55 #define CLK_TOP_DMPLL_D4 56 #define CLK_TOP_DMPLL_X2 57 #define CLK_TOP_TVDPLL 58 #define CLK_TOP_TVDPLL_D2 59 #define CLK_TOP_TVDPLL_D4 60 #define CLK_TOP_TVD2PLL 61 #define CLK_TOP_TVD2PLL_D2 62 #define CLK_TOP_HADDS2PLL_98M 63 #define CLK_TOP_HADDS2PLL_294M 64 #define CLK_TOP_HADDS2_FB 65 #define CLK_TOP_MIPIPLL_D2 66 #define CLK_TOP_MIPIPLL_D4 67 #define CLK_TOP_HDMIPLL 68 #define CLK_TOP_HDMIPLL_D2 69 #define CLK_TOP_HDMIPLL_D3 70 #define CLK_TOP_HDMI_SCL_RX 71 #define CLK_TOP_HDMI_0_PIX340M 72 #define CLK_TOP_HDMI_0_DEEP340M 73 #define CLK_TOP_HDMI_0_PLL340M 74 #define CLK_TOP_AUD1PLL_98M 75 #define CLK_TOP_AUD2PLL_90M 76 #define CLK_TOP_AUDPLL 77 #define CLK_TOP_AUDPLL_D4 78 #define CLK_TOP_AUDPLL_D8 79 #define CLK_TOP_AUDPLL_D16 80 #define CLK_TOP_AUDPLL_D24 81 #define CLK_TOP_ETHPLL_500M 82 #define CLK_TOP_VDECPLL 83 #define CLK_TOP_VENCPLL 84 #define CLK_TOP_MIPIPLL 85 #define CLK_TOP_ARMPLL_1P3G 86 87 #define CLK_TOP_MM_SEL 88 #define CLK_TOP_DDRPHYCFG_SEL 89 #define CLK_TOP_MEM_SEL 90 #define CLK_TOP_AXI_SEL 91 #define CLK_TOP_CAMTG_SEL 92 #define CLK_TOP_MFG_SEL 93 #define CLK_TOP_VDEC_SEL 94 #define CLK_TOP_PWM_SEL 95 #define CLK_TOP_MSDC30_0_SEL 96 #define CLK_TOP_USB20_SEL 97 #define CLK_TOP_SPI0_SEL 98 #define CLK_TOP_UART_SEL 99 #define CLK_TOP_AUDINTBUS_SEL 100 #define CLK_TOP_AUDIO_SEL 101 #define CLK_TOP_MSDC30_2_SEL 102 #define CLK_TOP_MSDC30_1_SEL 103 #define CLK_TOP_DPI1_SEL 104 #define CLK_TOP_DPI0_SEL 105 #define CLK_TOP_SCP_SEL 106 #define CLK_TOP_PMICSPI_SEL 107 #define CLK_TOP_APLL_SEL 108 #define CLK_TOP_HDMI_SEL 109 #define CLK_TOP_TVE_SEL 110 #define CLK_TOP_EMMC_HCLK_SEL 111 #define CLK_TOP_NFI2X_SEL 112 #define CLK_TOP_RTC_SEL 113 #define CLK_TOP_OSD_SEL 114 #define CLK_TOP_NR_SEL 115 #define CLK_TOP_DI_SEL 116 #define CLK_TOP_FLASH_SEL 117 #define CLK_TOP_ASM_M_SEL 118 #define CLK_TOP_ASM_I_SEL 119 #define CLK_TOP_INTDIR_SEL 120 #define CLK_TOP_HDMIRX_BIST_SEL 121 #define CLK_TOP_ETHIF_SEL 122 #define CLK_TOP_MS_CARD_SEL 123 #define CLK_TOP_ASM_H_SEL 124 #define CLK_TOP_SPI1_SEL 125 #define CLK_TOP_CMSYS_SEL 126 #define CLK_TOP_MSDC30_3_SEL 127 #define CLK_TOP_HDMIRX26_24_SEL 128 #define CLK_TOP_AUD2DVD_SEL 129 #define CLK_TOP_8BDAC_SEL 130 #define CLK_TOP_SPI2_SEL 131 #define CLK_TOP_AUD_MUX1_SEL 132 #define CLK_TOP_AUD_MUX2_SEL 133 #define CLK_TOP_AUDPLL_MUX_SEL 134 #define CLK_TOP_AUD_K1_SRC_SEL 135 #define CLK_TOP_AUD_K2_SRC_SEL 136 #define CLK_TOP_AUD_K3_SRC_SEL 137 #define CLK_TOP_AUD_K4_SRC_SEL 138 #define CLK_TOP_AUD_K5_SRC_SEL 139 #define CLK_TOP_AUD_K6_SRC_SEL 140 #define CLK_TOP_PADMCLK_SEL 141 #define CLK_TOP_AUD_EXTCK1_DIV 142 #define CLK_TOP_AUD_EXTCK2_DIV 143 #define CLK_TOP_AUD_MUX1_DIV 144 #define CLK_TOP_AUD_MUX2_DIV 145 #define CLK_TOP_AUD_K1_SRC_DIV 146 #define CLK_TOP_AUD_K2_SRC_DIV 147 #define CLK_TOP_AUD_K3_SRC_DIV 148 #define CLK_TOP_AUD_K4_SRC_DIV 149 #define CLK_TOP_AUD_K5_SRC_DIV 150 #define CLK_TOP_AUD_K6_SRC_DIV 151 #define CLK_TOP_AUD_I2S1_MCLK 152 #define CLK_TOP_AUD_I2S2_MCLK 153 #define CLK_TOP_AUD_I2S3_MCLK 154 #define CLK_TOP_AUD_I2S4_MCLK 155 #define CLK_TOP_AUD_I2S5_MCLK 156 #define CLK_TOP_AUD_I2S6_MCLK 157 #define CLK_TOP_AUD_48K_TIMING 158 #define CLK_TOP_AUD_44K_TIMING 159 160 #define CLK_TOP_32K_INTERNAL 161 #define CLK_TOP_32K_EXTERNAL 162 #define CLK_TOP_CLK26M_D8 163 #define CLK_TOP_8BDAC 164 #define CLK_TOP_WBG_DIG_416M 165 #define CLK_TOP_DPI 166 #define CLK_TOP_DSI0_LNTC_DSI 167 #define CLK_TOP_AUD_EXT1 168 #define CLK_TOP_AUD_EXT2 169 #define CLK_TOP_NFI1X_PAD 170 #define CLK_TOP_AXISEL_D4 171 #define CLK_TOP_NR 172 173 /* APMIXEDSYS */ 174 175 #define CLK_APMIXED_ARMPLL 176 #define CLK_APMIXED_MAINPLL 177 #define CLK_APMIXED_UNIVPLL 178 #define CLK_APMIXED_MMPLL 179 #define CLK_APMIXED_MSDCPLL 180 #define CLK_APMIXED_TVDPLL 181 #define CLK_APMIXED_AUD1PLL 182 #define CLK_APMIXED_TRGPLL 183 #define CLK_APMIXED_ETHPLL 184 #define CLK_APMIXED_VDECPLL 185 #define CLK_APMIXED_HADDS2PLL 186 #define CLK_APMIXED_AUD2PLL 187 #define CLK_APMIXED_TVD2PLL 188 #define CLK_APMIXED_HDMI_REF 189 #define CLK_APMIXED_NR 190 191 /* DDRPHY */ 192 193 #define CLK_DDRPHY_VENCPLL 194 #define CLK_DDRPHY_NR 195 196 /* INFRACFG */ 197 198 #define CLK_INFRA_DBG 199 #define CLK_INFRA_SMI 200 #define CLK_INFRA_QAXI_CM4 201 #define CLK_INFRA_AUD_SPLIN_B 202 #define CLK_INFRA_AUDIO 203 #define CLK_INFRA_EFUSE 204 #define CLK_INFRA_L2C_SRAM 205 #define CLK_INFRA_M4U 206 #define CLK_INFRA_CONNMCU 207 #define CLK_INFRA_TRNG 208 #define CLK_INFRA_RAMBUFIF 209 #define CLK_INFRA_CPUM 210 #define CLK_INFRA_KP 211 #define CLK_INFRA_CEC 212 #define CLK_INFRA_IRRX 213 #define CLK_INFRA_PMICSPI 214 #define CLK_INFRA_PMICWRAP 215 #define CLK_INFRA_DDCCI 216 #define CLK_INFRA_CLK_13M 217 #define CLK_INFRA_CPUSEL 218 #define CLK_INFRA_NR 219 220 /* PERICFG */ 221 222 #define CLK_PERI_NFI 223 #define CLK_PERI_THERM 224 #define CLK_PERI_PWM1 225 #define CLK_PERI_PWM2 226 #define CLK_PERI_PWM3 227 #define CLK_PERI_PWM4 228 #define CLK_PERI_PWM5 229 #define CLK_PERI_PWM6 230 #define CLK_PERI_PWM7 231 #define CLK_PERI_PWM 232 #define CLK_PERI_USB0 233 #define CLK_PERI_USB1 234 #define CLK_PERI_AP_DMA 235 #define CLK_PERI_MSDC30_0 236 #define CLK_PERI_MSDC30_1 237 #define CLK_PERI_MSDC30_2 238 #define CLK_PERI_MSDC30_3 239 #define CLK_PERI_MSDC50_3 240 #define CLK_PERI_NLI 241 #define CLK_PERI_UART0 242 #define CLK_PERI_UART1 243 #define CLK_PERI_UART2 244 #define CLK_PERI_UART3 245 #define CLK_PERI_BTIF 246 #define CLK_PERI_I2C0 247 #define CLK_PERI_I2C1 248 #define CLK_PERI_I2C2 249 #define CLK_PERI_I2C3 250 #define CLK_PERI_AUXADC 251 #define CLK_PERI_SPI0 252 #define CLK_PERI_ETH 253 #define CLK_PERI_USB0_MCU 254 255 #define CLK_PERI_USB1_MCU 256 #define CLK_PERI_USB_SLV 257 #define CLK_PERI_GCPU 258 #define CLK_PERI_NFI_ECC 259 #define CLK_PERI_NFI_PAD 260 #define CLK_PERI_FLASH 261 #define CLK_PERI_HOST89_INT 262 #define CLK_PERI_HOST89_SPI 263 #define CLK_PERI_HOST89_DVD 264 #define CLK_PERI_SPI1 265 #define CLK_PERI_SPI2 266 #define CLK_PERI_FCI 267 268 #define CLK_PERI_UART0_SEL 269 #define CLK_PERI_UART1_SEL 270 #define CLK_PERI_UART2_SEL 271 #define CLK_PERI_UART3_SEL 272 #define CLK_PERI_NR 273 274 /* AUDIO */ 275 276 #define CLK_AUD_AFE 277 #define CLK_AUD_LRCK_DETECT 278 #define CLK_AUD_I2S 279 #define CLK_AUD_APLL_TUNER 280 #define CLK_AUD_HDMI 281 #define CLK_AUD_SPDF 282 #define CLK_AUD_SPDF2 283 #define CLK_AUD_APLL 284 #define CLK_AUD_TML 285 #define CLK_AUD_AHB_IDLE_EXT 286 #define CLK_AUD_AHB_IDLE_INT 287 288 #define CLK_AUD_I2SIN1 289 #define CLK_AUD_I2SIN2 290 #define CLK_AUD_I2SIN3 291 #define CLK_AUD_I2SIN4 292 #define CLK_AUD_I2SIN5 293 #define CLK_AUD_I2SIN6 294 #define CLK_AUD_I2SO1 295 #define CLK_AUD_I2SO2 296 #define CLK_AUD_I2SO3 297 #define CLK_AUD_I2SO4 298 #define CLK_AUD_I2SO5 299 #define CLK_AUD_I2SO6 300 #define CLK_AUD_ASRCI1 301 #define CLK_AUD_ASRCI2 302 #define CLK_AUD_ASRCO1 303 #define CLK_AUD_ASRCO2 304 #define CLK_AUD_ASRC11 305 #define CLK_AUD_ASRC12 306 #define CLK_AUD_HDMIRX 307 #define CLK_AUD_INTDIR 308 #define CLK_AUD_A1SYS 309 #define CLK_AUD_A2SYS 310 #define CLK_AUD_AFE_CONN 311 #define CLK_AUD_AFE_PCMIF 312 #define CLK_AUD_AFE_MRGIF 313 314 #define CLK_AUD_MMIF_UL1 315 #define CLK_AUD_MMIF_UL2 316 #define CLK_AUD_MMIF_UL3 317 #define CLK_AUD_MMIF_UL4 318 #define CLK_AUD_MMIF_UL5 319 #define CLK_AUD_MMIF_UL6 320 #define CLK_AUD_MMIF_DL1 321 #define CLK_AUD_MMIF_DL2 322 #define CLK_AUD_MMIF_DL3 323 #define CLK_AUD_MMIF_DL4 324 #define CLK_AUD_MMIF_DL5 325 #define CLK_AUD_MMIF_DL6 326 #define CLK_AUD_MMIF_DLMCH 327 #define CLK_AUD_MMIF_ARB1 328 #define CLK_AUD_MMIF_AWB1 329 #define CLK_AUD_MMIF_AWB2 330 #define CLK_AUD_MMIF_DAI 331 332 #define CLK_AUD_DMIC1 333 #define CLK_AUD_DMIC2 334 #define CLK_AUD_ASRCI3 335 #define CLK_AUD_ASRCI4 336 #define CLK_AUD_ASRCI5 337 #define CLK_AUD_ASRCI6 338 #define CLK_AUD_ASRCO3 339 #define CLK_AUD_ASRCO4 340 #define CLK_AUD_ASRCO5 341 #define CLK_AUD_ASRCO6 342 #define CLK_AUD_MEM_ASRC1 343 #define CLK_AUD_MEM_ASRC2 344 #define CLK_AUD_MEM_ASRC3 345 #define CLK_AUD_MEM_ASRC4 346 #define CLK_AUD_MEM_ASRC5 347 #define CLK_AUD_DSD_ENC 348 #define CLK_AUD_ASRC_BRG 349 #define CLK_AUD_NR 350 351 /* MMSYS */ 352 353 #define CLK_MM_SMI_COMMON 354 #define CLK_MM_SMI_LARB0 355 #define CLK_MM_CMDQ 356 #define CLK_MM_MUTEX 357 #define CLK_MM_DISP_COLOR 358 #define CLK_MM_DISP_BLS 359 #define CLK_MM_DISP_WDMA 360 #define CLK_MM_DISP_RDMA 361 #define CLK_MM_DISP_OVL 362 #define CLK_MM_MDP_TDSHP 363 #define CLK_MM_MDP_WROT 364 #define CLK_MM_MDP_WDMA 365 #define CLK_MM_MDP_RSZ1 366 #define CLK_MM_MDP_RSZ0 367 #define CLK_MM_MDP_RDMA 368 #define CLK_MM_MDP_BLS_26M 369 #define CLK_MM_CAM_MDP 370 #define CLK_MM_FAKE_ENG 371 #define CLK_MM_MUTEX_32K 372 #define CLK_MM_DISP_RDMA1 373 #define CLK_MM_DISP_UFOE 374 375 #define CLK_MM_DSI_ENGINE 376 #define CLK_MM_DSI_DIG 377 #define CLK_MM_DPI_DIGL 378 #define CLK_MM_DPI_ENGINE 379 #define CLK_MM_DPI1_DIGL 380 #define CLK_MM_DPI1_ENGINE 381 #define CLK_MM_TVE_OUTPUT 382 #define CLK_MM_TVE_INPUT 383 #define CLK_MM_HDMI_PIXEL 384 #define CLK_MM_HDMI_PLL 385 #define CLK_MM_HDMI_AUDIO 386 #define CLK_MM_HDMI_SPDIF 387 #define CLK_MM_TVE_FMM 388 #define CLK_MM_NR 389 390 /* IMGSYS */ 391 392 #define CLK_IMG_SMI_COMM 393 #define CLK_IMG_RESZ 394 #define CLK_IMG_JPGDEC_SMI 395 #define CLK_IMG_JPGDEC 396 #define CLK_IMG_VENC_LT 397 #define CLK_IMG_VENC 398 #define CLK_IMG_NR 399 400 /* VDEC */ 401 402 #define CLK_VDEC_CKGEN 403 #define CLK_VDEC_LARB 404 #define CLK_VDEC_NR 405 406 /* HIFSYS */ 407 408 #define CLK_HIFSYS_USB0PHY 409 #define CLK_HIFSYS_USB1PHY 410 #define CLK_HIFSYS_PCIE0 411 #define CLK_HIFSYS_PCIE1 412 #define CLK_HIFSYS_PCIE2 413 #define CLK_HIFSYS_NR 414 415 /* ETHSYS */ 416 #define CLK_ETHSYS_HSDMA 417 #define CLK_ETHSYS_ESW 418 #define CLK_ETHSYS_GP2 419 #define CLK_ETHSYS_GP1 420 #define CLK_ETHSYS_PCM 421 #define CLK_ETHSYS_GDMA 422 #define CLK_ETHSYS_I2S 423 #define CLK_ETHSYS_CRYPTO 424 #define CLK_ETHSYS_NR 425 426 /* G3DSYS */ 427 #define CLK_G3DSYS_CORE 428 #define CLK_G3DSYS_NR 429 430 /* BDP */ 431 432 #define CLK_BDP_BRG_BA 433 #define CLK_BDP_BRG_DRAM 434 #define CLK_BDP_LARB_DRAM 435 #define CLK_BDP_WR_VDI_PXL 436 #define CLK_BDP_WR_VDI_DRAM 437 #define CLK_BDP_WR_B 438 #define CLK_BDP_DGI_IN 439 #define CLK_BDP_DGI_OUT 440 #define CLK_BDP_FMT_MAST_27 441 #define CLK_BDP_FMT_B 442 #define CLK_BDP_OSD_B 443 #define CLK_BDP_OSD_DRAM 444 #define CLK_BDP_OSD_AGENT 445 #define CLK_BDP_OSD_PXL 446 #define CLK_BDP_RLE_B 447 #define CLK_BDP_RLE_AGENT 448 #define CLK_BDP_RLE_DRAM 449 #define CLK_BDP_F27M 450 #define CLK_BDP_F27M_VDOUT 451 #define CLK_BDP_F27_74_74 452 #define CLK_BDP_F2FS 453 #define CLK_BDP_F2FS74_148 454 #define CLK_BDP_FB 455 #define CLK_BDP_VDO_DRAM 456 #define CLK_BDP_VDO_2FS 457 #define CLK_BDP_VDO_B 458 #define CLK_BDP_WR_DI_PXL 459 #define CLK_BDP_WR_DI_DRAM 460 #define CLK_BDP_WR_DI_B 461 #define CLK_BDP_NR_PXL 462 #define CLK_BDP_NR_DRAM 463 #define CLK_BDP_NR_B 464 465 #define CLK_BDP_RX_F 466 #define CLK_BDP_RX_X 467 #define CLK_BDP_RXPDT 468 #define CLK_BDP_RX_CSCL_N 469 #define CLK_BDP_RX_CSCL 470 #define CLK_BDP_RX_DDCSCL_N 471 #define CLK_BDP_RX_DDCSCL 472 #define CLK_BDP_RX_VCO 473 #define CLK_BDP_RX_DP 474 #define CLK_BDP_RX_P 475 #define CLK_BDP_RX_M 476 #define CLK_BDP_RX_PLL 477 #define CLK_BDP_BRG_RT_B 478 #define CLK_BDP_BRG_RT_DRAM 479 #define CLK_BDP_LARBRT_DRAM 480 #define CLK_BDP_TMDS_SYN 481 #define CLK_BDP_HDMI_MON 482 #define CLK_BDP_NR 483 484 #endif /* _DT_BINDINGS_CLK_MT2701_H */ 485
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