1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Wendell Lin <wendell.lin@mediatek.c 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_MT6779_H 8 #define _DT_BINDINGS_CLK_MT6779_H 9 10 /* TOPCKGEN */ 11 #define CLK_TOP_AXI 1 12 #define CLK_TOP_MM 2 13 #define CLK_TOP_CAM 3 14 #define CLK_TOP_MFG 4 15 #define CLK_TOP_CAMTG 5 16 #define CLK_TOP_UART 6 17 #define CLK_TOP_SPI 7 18 #define CLK_TOP_MSDC50_0_HCLK 8 19 #define CLK_TOP_MSDC50_0 9 20 #define CLK_TOP_MSDC30_1 10 21 #define CLK_TOP_MSDC30_2 11 22 #define CLK_TOP_AUD 12 23 #define CLK_TOP_AUD_INTBUS 13 24 #define CLK_TOP_FPWRAP_ULPOSC 14 25 #define CLK_TOP_SCP 15 26 #define CLK_TOP_ATB 16 27 #define CLK_TOP_SSPM 17 28 #define CLK_TOP_DPI0 18 29 #define CLK_TOP_SCAM 19 30 #define CLK_TOP_AUD_1 20 31 #define CLK_TOP_AUD_2 21 32 #define CLK_TOP_DISP_PWM 22 33 #define CLK_TOP_SSUSB_TOP_XHCI 23 34 #define CLK_TOP_USB_TOP 24 35 #define CLK_TOP_SPM 25 36 #define CLK_TOP_I2C 26 37 #define CLK_TOP_F52M_MFG 27 38 #define CLK_TOP_SENINF 28 39 #define CLK_TOP_DXCC 29 40 #define CLK_TOP_CAMTG2 30 41 #define CLK_TOP_AUD_ENG1 31 42 #define CLK_TOP_AUD_ENG2 32 43 #define CLK_TOP_FAES_UFSFDE 33 44 #define CLK_TOP_FUFS 34 45 #define CLK_TOP_IMG 35 46 #define CLK_TOP_DSP 36 47 #define CLK_TOP_DSP1 37 48 #define CLK_TOP_DSP2 38 49 #define CLK_TOP_IPU_IF 39 50 #define CLK_TOP_CAMTG3 40 51 #define CLK_TOP_CAMTG4 41 52 #define CLK_TOP_PMICSPI 42 53 #define CLK_TOP_MAINPLL_CK 43 54 #define CLK_TOP_MAINPLL_D2 44 55 #define CLK_TOP_MAINPLL_D3 45 56 #define CLK_TOP_MAINPLL_D5 46 57 #define CLK_TOP_MAINPLL_D7 47 58 #define CLK_TOP_MAINPLL_D2_D2 48 59 #define CLK_TOP_MAINPLL_D2_D4 49 60 #define CLK_TOP_MAINPLL_D2_D8 50 61 #define CLK_TOP_MAINPLL_D2_D16 51 62 #define CLK_TOP_MAINPLL_D3_D2 52 63 #define CLK_TOP_MAINPLL_D3_D4 53 64 #define CLK_TOP_MAINPLL_D3_D8 54 65 #define CLK_TOP_MAINPLL_D5_D2 55 66 #define CLK_TOP_MAINPLL_D5_D4 56 67 #define CLK_TOP_MAINPLL_D7_D2 57 68 #define CLK_TOP_MAINPLL_D7_D4 58 69 #define CLK_TOP_UNIVPLL_CK 59 70 #define CLK_TOP_UNIVPLL_D2 60 71 #define CLK_TOP_UNIVPLL_D3 61 72 #define CLK_TOP_UNIVPLL_D5 62 73 #define CLK_TOP_UNIVPLL_D7 63 74 #define CLK_TOP_UNIVPLL_D2_D2 64 75 #define CLK_TOP_UNIVPLL_D2_D4 65 76 #define CLK_TOP_UNIVPLL_D2_D8 66 77 #define CLK_TOP_UNIVPLL_D3_D2 67 78 #define CLK_TOP_UNIVPLL_D3_D4 68 79 #define CLK_TOP_UNIVPLL_D3_D8 69 80 #define CLK_TOP_UNIVPLL_D5_D2 70 81 #define CLK_TOP_UNIVPLL_D5_D4 71 82 #define CLK_TOP_UNIVPLL_D5_D8 72 83 #define CLK_TOP_APLL1_CK 73 84 #define CLK_TOP_APLL1_D2 74 85 #define CLK_TOP_APLL1_D4 75 86 #define CLK_TOP_APLL1_D8 76 87 #define CLK_TOP_APLL2_CK 77 88 #define CLK_TOP_APLL2_D2 78 89 #define CLK_TOP_APLL2_D4 79 90 #define CLK_TOP_APLL2_D8 80 91 #define CLK_TOP_TVDPLL_CK 81 92 #define CLK_TOP_TVDPLL_D2 82 93 #define CLK_TOP_TVDPLL_D4 83 94 #define CLK_TOP_TVDPLL_D8 84 95 #define CLK_TOP_TVDPLL_D16 85 96 #define CLK_TOP_MSDCPLL_CK 86 97 #define CLK_TOP_MSDCPLL_D2 87 98 #define CLK_TOP_MSDCPLL_D4 88 99 #define CLK_TOP_MSDCPLL_D8 89 100 #define CLK_TOP_MSDCPLL_D16 90 101 #define CLK_TOP_AD_OSC_CK 91 102 #define CLK_TOP_OSC_D2 92 103 #define CLK_TOP_OSC_D4 93 104 #define CLK_TOP_OSC_D8 94 105 #define CLK_TOP_OSC_D16 95 106 #define CLK_TOP_F26M_CK_D2 96 107 #define CLK_TOP_MFGPLL_CK 97 108 #define CLK_TOP_UNIVP_192M_CK 98 109 #define CLK_TOP_UNIVP_192M_D2 99 110 #define CLK_TOP_UNIVP_192M_D4 100 111 #define CLK_TOP_UNIVP_192M_D8 101 112 #define CLK_TOP_UNIVP_192M_D16 102 113 #define CLK_TOP_UNIVP_192M_D32 103 114 #define CLK_TOP_MMPLL_CK 104 115 #define CLK_TOP_MMPLL_D4 105 116 #define CLK_TOP_MMPLL_D4_D2 106 117 #define CLK_TOP_MMPLL_D4_D4 107 118 #define CLK_TOP_MMPLL_D5 108 119 #define CLK_TOP_MMPLL_D5_D2 109 120 #define CLK_TOP_MMPLL_D5_D4 110 121 #define CLK_TOP_MMPLL_D6 111 122 #define CLK_TOP_MMPLL_D7 112 123 #define CLK_TOP_CLK26M 113 124 #define CLK_TOP_CLK13M 114 125 #define CLK_TOP_ADSP 115 126 #define CLK_TOP_DPMAIF 116 127 #define CLK_TOP_VENC 117 128 #define CLK_TOP_VDEC 118 129 #define CLK_TOP_CAMTM 119 130 #define CLK_TOP_PWM 120 131 #define CLK_TOP_ADSPPLL_CK 121 132 #define CLK_TOP_I2S0_M_SEL 122 133 #define CLK_TOP_I2S1_M_SEL 123 134 #define CLK_TOP_I2S2_M_SEL 124 135 #define CLK_TOP_I2S3_M_SEL 125 136 #define CLK_TOP_I2S4_M_SEL 126 137 #define CLK_TOP_I2S5_M_SEL 127 138 #define CLK_TOP_APLL12_DIV0 128 139 #define CLK_TOP_APLL12_DIV1 129 140 #define CLK_TOP_APLL12_DIV2 130 141 #define CLK_TOP_APLL12_DIV3 131 142 #define CLK_TOP_APLL12_DIV4 132 143 #define CLK_TOP_APLL12_DIVB 133 144 #define CLK_TOP_APLL12_DIV5 134 145 #define CLK_TOP_IPE 135 146 #define CLK_TOP_DPE 136 147 #define CLK_TOP_CCU 137 148 #define CLK_TOP_DSP3 138 149 #define CLK_TOP_SENINF1 139 150 #define CLK_TOP_SENINF2 140 151 #define CLK_TOP_AUD_H 141 152 #define CLK_TOP_CAMTG5 142 153 #define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143 154 #define CLK_TOP_AD_OSC2_CK 144 155 #define CLK_TOP_OSC2_D2 145 156 #define CLK_TOP_OSC2_D3 146 157 #define CLK_TOP_FMEM_466M_CK 147 158 #define CLK_TOP_ADSPPLL_D4 148 159 #define CLK_TOP_ADSPPLL_D5 149 160 #define CLK_TOP_ADSPPLL_D6 150 161 #define CLK_TOP_OSC_D10 151 162 #define CLK_TOP_UNIVPLL_D3_D16 152 163 #define CLK_TOP_NR_CLK 153 164 165 /* APMIXED */ 166 #define CLK_APMIXED_ARMPLL_LL 1 167 #define CLK_APMIXED_ARMPLL_BL 2 168 #define CLK_APMIXED_ARMPLL_BB 3 169 #define CLK_APMIXED_CCIPLL 4 170 #define CLK_APMIXED_MAINPLL 5 171 #define CLK_APMIXED_UNIV2PLL 6 172 #define CLK_APMIXED_MSDCPLL 7 173 #define CLK_APMIXED_ADSPPLL 8 174 #define CLK_APMIXED_MMPLL 9 175 #define CLK_APMIXED_MFGPLL 10 176 #define CLK_APMIXED_TVDPLL 11 177 #define CLK_APMIXED_APLL1 12 178 #define CLK_APMIXED_APLL2 13 179 #define CLK_APMIXED_SSUSB26M 14 180 #define CLK_APMIXED_APPLL26M 15 181 #define CLK_APMIXED_MIPIC0_26M 16 182 #define CLK_APMIXED_MDPLLGP26M 17 183 #define CLK_APMIXED_MM_F26M 18 184 #define CLK_APMIXED_UFS26M 19 185 #define CLK_APMIXED_MIPIC1_26M 20 186 #define CLK_APMIXED_MEMPLL26M 21 187 #define CLK_APMIXED_CLKSQ_LVPLL_26M 22 188 #define CLK_APMIXED_MIPID0_26M 23 189 #define CLK_APMIXED_MIPID1_26M 24 190 #define CLK_APMIXED_NR_CLK 25 191 192 /* CAMSYS */ 193 #define CLK_CAM_LARB10 1 194 #define CLK_CAM_DFP_VAD 2 195 #define CLK_CAM_LARB11 3 196 #define CLK_CAM_LARB9 4 197 #define CLK_CAM_CAM 5 198 #define CLK_CAM_CAMTG 6 199 #define CLK_CAM_SENINF 7 200 #define CLK_CAM_CAMSV0 8 201 #define CLK_CAM_CAMSV1 9 202 #define CLK_CAM_CAMSV2 10 203 #define CLK_CAM_CAMSV3 11 204 #define CLK_CAM_CCU 12 205 #define CLK_CAM_FAKE_ENG 13 206 #define CLK_CAM_NR_CLK 14 207 208 /* INFRA */ 209 #define CLK_INFRA_PMIC_TMR 1 210 #define CLK_INFRA_PMIC_AP 2 211 #define CLK_INFRA_PMIC_MD 3 212 #define CLK_INFRA_PMIC_CONN 4 213 #define CLK_INFRA_SCPSYS 5 214 #define CLK_INFRA_SEJ 6 215 #define CLK_INFRA_APXGPT 7 216 #define CLK_INFRA_ICUSB 8 217 #define CLK_INFRA_GCE 9 218 #define CLK_INFRA_THERM 10 219 #define CLK_INFRA_I2C0 11 220 #define CLK_INFRA_I2C1 12 221 #define CLK_INFRA_I2C2 13 222 #define CLK_INFRA_I2C3 14 223 #define CLK_INFRA_PWM_HCLK 15 224 #define CLK_INFRA_PWM1 16 225 #define CLK_INFRA_PWM2 17 226 #define CLK_INFRA_PWM3 18 227 #define CLK_INFRA_PWM4 19 228 #define CLK_INFRA_PWM 20 229 #define CLK_INFRA_UART0 21 230 #define CLK_INFRA_UART1 22 231 #define CLK_INFRA_UART2 23 232 #define CLK_INFRA_UART3 24 233 #define CLK_INFRA_GCE_26M 25 234 #define CLK_INFRA_CQ_DMA_FPC 26 235 #define CLK_INFRA_BTIF 27 236 #define CLK_INFRA_SPI0 28 237 #define CLK_INFRA_MSDC0 29 238 #define CLK_INFRA_MSDC1 30 239 #define CLK_INFRA_MSDC2 31 240 #define CLK_INFRA_MSDC0_SCK 32 241 #define CLK_INFRA_DVFSRC 33 242 #define CLK_INFRA_GCPU 34 243 #define CLK_INFRA_TRNG 35 244 #define CLK_INFRA_AUXADC 36 245 #define CLK_INFRA_CPUM 37 246 #define CLK_INFRA_CCIF1_AP 38 247 #define CLK_INFRA_CCIF1_MD 39 248 #define CLK_INFRA_AUXADC_MD 40 249 #define CLK_INFRA_MSDC1_SCK 41 250 #define CLK_INFRA_MSDC2_SCK 42 251 #define CLK_INFRA_AP_DMA 43 252 #define CLK_INFRA_XIU 44 253 #define CLK_INFRA_DEVICE_APC 45 254 #define CLK_INFRA_CCIF_AP 46 255 #define CLK_INFRA_DEBUGSYS 47 256 #define CLK_INFRA_AUD 48 257 #define CLK_INFRA_CCIF_MD 49 258 #define CLK_INFRA_DXCC_SEC_CORE 50 259 #define CLK_INFRA_DXCC_AO 51 260 #define CLK_INFRA_DRAMC_F26M 52 261 #define CLK_INFRA_IRTX 53 262 #define CLK_INFRA_DISP_PWM 54 263 #define CLK_INFRA_DPMAIF_CK 55 264 #define CLK_INFRA_AUD_26M_BCLK 56 265 #define CLK_INFRA_SPI1 57 266 #define CLK_INFRA_I2C4 58 267 #define CLK_INFRA_MODEM_TEMP_SHARE 59 268 #define CLK_INFRA_SPI2 60 269 #define CLK_INFRA_SPI3 61 270 #define CLK_INFRA_UNIPRO_SCK 62 271 #define CLK_INFRA_UNIPRO_TICK 63 272 #define CLK_INFRA_UFS_MP_SAP_BCLK 64 273 #define CLK_INFRA_MD32_BCLK 65 274 #define CLK_INFRA_SSPM 66 275 #define CLK_INFRA_UNIPRO_MBIST 67 276 #define CLK_INFRA_SSPM_BUS_HCLK 68 277 #define CLK_INFRA_I2C5 69 278 #define CLK_INFRA_I2C5_ARBITER 70 279 #define CLK_INFRA_I2C5_IMM 71 280 #define CLK_INFRA_I2C1_ARBITER 72 281 #define CLK_INFRA_I2C1_IMM 73 282 #define CLK_INFRA_I2C2_ARBITER 74 283 #define CLK_INFRA_I2C2_IMM 75 284 #define CLK_INFRA_SPI4 76 285 #define CLK_INFRA_SPI5 77 286 #define CLK_INFRA_CQ_DMA 78 287 #define CLK_INFRA_UFS 79 288 #define CLK_INFRA_AES_UFSFDE 80 289 #define CLK_INFRA_UFS_TICK 81 290 #define CLK_INFRA_MSDC0_SELF 82 291 #define CLK_INFRA_MSDC1_SELF 83 292 #define CLK_INFRA_MSDC2_SELF 84 293 #define CLK_INFRA_SSPM_26M_SELF 85 294 #define CLK_INFRA_SSPM_32K_SELF 86 295 #define CLK_INFRA_UFS_AXI 87 296 #define CLK_INFRA_I2C6 88 297 #define CLK_INFRA_AP_MSDC0 89 298 #define CLK_INFRA_MD_MSDC0 90 299 #define CLK_INFRA_USB 91 300 #define CLK_INFRA_DEVMPU_BCLK 92 301 #define CLK_INFRA_CCIF2_AP 93 302 #define CLK_INFRA_CCIF2_MD 94 303 #define CLK_INFRA_CCIF3_AP 95 304 #define CLK_INFRA_CCIF3_MD 96 305 #define CLK_INFRA_SEJ_F13M 97 306 #define CLK_INFRA_AES_BCLK 98 307 #define CLK_INFRA_I2C7 99 308 #define CLK_INFRA_I2C8 100 309 #define CLK_INFRA_FBIST2FPC 101 310 #define CLK_INFRA_CCIF4_AP 102 311 #define CLK_INFRA_CCIF4_MD 103 312 #define CLK_INFRA_FADSP 104 313 #define CLK_INFRA_SSUSB_XHCI 105 314 #define CLK_INFRA_SPI6 106 315 #define CLK_INFRA_SPI7 107 316 #define CLK_INFRA_NR_CLK 108 317 318 /* MFGCFG */ 319 #define CLK_MFGCFG_BG3D 1 320 #define CLK_MFGCFG_NR_CLK 2 321 322 /* IMG */ 323 #define CLK_IMG_WPE_A 1 324 #define CLK_IMG_MFB 2 325 #define CLK_IMG_DIP 3 326 #define CLK_IMG_LARB6 4 327 #define CLK_IMG_LARB5 5 328 #define CLK_IMG_NR_CLK 6 329 330 /* IPE */ 331 #define CLK_IPE_LARB7 1 332 #define CLK_IPE_LARB8 2 333 #define CLK_IPE_SMI_SUBCOM 3 334 #define CLK_IPE_FD 4 335 #define CLK_IPE_FE 5 336 #define CLK_IPE_RSC 6 337 #define CLK_IPE_DPE 7 338 #define CLK_IPE_NR_CLK 8 339 340 /* MM_CONFIG */ 341 #define CLK_MM_SMI_COMMON 1 342 #define CLK_MM_SMI_LARB0 2 343 #define CLK_MM_SMI_LARB1 3 344 #define CLK_MM_GALS_COMM0 4 345 #define CLK_MM_GALS_COMM1 5 346 #define CLK_MM_GALS_CCU2MM 6 347 #define CLK_MM_GALS_IPU12MM 7 348 #define CLK_MM_GALS_IMG2MM 8 349 #define CLK_MM_GALS_CAM2MM 9 350 #define CLK_MM_GALS_IPU2MM 10 351 #define CLK_MM_MDP_DL_TXCK 11 352 #define CLK_MM_IPU_DL_TXCK 12 353 #define CLK_MM_MDP_RDMA0 13 354 #define CLK_MM_MDP_RDMA1 14 355 #define CLK_MM_MDP_RSZ0 15 356 #define CLK_MM_MDP_RSZ1 16 357 #define CLK_MM_MDP_TDSHP 17 358 #define CLK_MM_MDP_WROT0 18 359 #define CLK_MM_FAKE_ENG 19 360 #define CLK_MM_DISP_OVL0 20 361 #define CLK_MM_DISP_OVL0_2L 21 362 #define CLK_MM_DISP_OVL1_2L 22 363 #define CLK_MM_DISP_RDMA0 23 364 #define CLK_MM_DISP_RDMA1 24 365 #define CLK_MM_DISP_WDMA0 25 366 #define CLK_MM_DISP_COLOR0 26 367 #define CLK_MM_DISP_CCORR0 27 368 #define CLK_MM_DISP_AAL0 28 369 #define CLK_MM_DISP_GAMMA0 29 370 #define CLK_MM_DISP_DITHER0 30 371 #define CLK_MM_DISP_SPLIT 31 372 #define CLK_MM_DSI0_MM_CK 32 373 #define CLK_MM_DSI0_IF_CK 33 374 #define CLK_MM_DPI_MM_CK 34 375 #define CLK_MM_DPI_IF_CK 35 376 #define CLK_MM_FAKE_ENG2 36 377 #define CLK_MM_MDP_DL_RX_CK 37 378 #define CLK_MM_IPU_DL_RX_CK 38 379 #define CLK_MM_26M 39 380 #define CLK_MM_MM_R2Y 40 381 #define CLK_MM_DISP_RSZ 41 382 #define CLK_MM_MDP_WDMA0 42 383 #define CLK_MM_MDP_AAL 43 384 #define CLK_MM_MDP_HDR 44 385 #define CLK_MM_DBI_MM_CK 45 386 #define CLK_MM_DBI_IF_CK 46 387 #define CLK_MM_MDP_WROT1 47 388 #define CLK_MM_DISP_POSTMASK0 48 389 #define CLK_MM_DISP_HRT_BW 49 390 #define CLK_MM_DISP_OVL_FBDC 50 391 #define CLK_MM_NR_CLK 51 392 393 /* VDEC_GCON */ 394 #define CLK_VDEC_VDEC 1 395 #define CLK_VDEC_LARB1 2 396 #define CLK_VDEC_GCON_NR_CLK 3 397 398 /* VENC_GCON */ 399 #define CLK_VENC_GCON_LARB 1 400 #define CLK_VENC_GCON_VENC 2 401 #define CLK_VENC_GCON_JPGENC 3 402 #define CLK_VENC_GCON_GALS 4 403 #define CLK_VENC_GCON_NR_CLK 5 404 405 /* AUD */ 406 #define CLK_AUD_AFE 1 407 #define CLK_AUD_22M 2 408 #define CLK_AUD_24M 3 409 #define CLK_AUD_APLL2_TUNER 4 410 #define CLK_AUD_APLL_TUNER 5 411 #define CLK_AUD_TDM 6 412 #define CLK_AUD_ADC 7 413 #define CLK_AUD_DAC 8 414 #define CLK_AUD_DAC_PREDIS 9 415 #define CLK_AUD_TML 10 416 #define CLK_AUD_NLE 11 417 #define CLK_AUD_I2S1_BCLK_SW 12 418 #define CLK_AUD_I2S2_BCLK_SW 13 419 #define CLK_AUD_I2S3_BCLK_SW 14 420 #define CLK_AUD_I2S4_BCLK_SW 15 421 #define CLK_AUD_I2S5_BCLK_SW 16 422 #define CLK_AUD_CONN_I2S_ASRC 17 423 #define CLK_AUD_GENERAL1_ASRC 18 424 #define CLK_AUD_GENERAL2_ASRC 19 425 #define CLK_AUD_DAC_HIRES 20 426 #define CLK_AUD_PDN_ADDA6_ADC 21 427 #define CLK_AUD_ADC_HIRES 22 428 #define CLK_AUD_ADC_HIRES_TML 23 429 #define CLK_AUD_ADDA6_ADC_HIRES 24 430 #define CLK_AUD_3RD_DAC 25 431 #define CLK_AUD_3RD_DAC_PREDIS 26 432 #define CLK_AUD_3RD_DAC_TML 27 433 #define CLK_AUD_3RD_DAC_HIRES 28 434 #define CLK_AUD_NR_CLK 29 435 436 #endif /* _DT_BINDINGS_CLK_MT6779_H */ 437
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