1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Kevin Chen <kevin-cw.chen@mediatek. 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_MT6797_H 8 #define _DT_BINDINGS_CLK_MT6797_H 9 10 /* TOPCKGEN */ 11 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 12 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 13 #define CLK_TOP_MUX_AXI 14 #define CLK_TOP_MUX_MEM 15 #define CLK_TOP_MUX_DDRPHYCFG 16 #define CLK_TOP_MUX_MM 17 #define CLK_TOP_MUX_PWM 18 #define CLK_TOP_MUX_VDEC 19 #define CLK_TOP_MUX_VENC 20 #define CLK_TOP_MUX_MFG 21 #define CLK_TOP_MUX_CAMTG 22 #define CLK_TOP_MUX_UART 23 #define CLK_TOP_MUX_SPI 24 #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 25 #define CLK_TOP_MUX_USB20 26 #define CLK_TOP_MUX_MSDC50_0_HCLK 27 #define CLK_TOP_MUX_MSDC50_0 28 #define CLK_TOP_MUX_MSDC30_1 29 #define CLK_TOP_MUX_MSDC30_2 30 #define CLK_TOP_MUX_AUDIO 31 #define CLK_TOP_MUX_AUD_INTBUS 32 #define CLK_TOP_MUX_PMICSPI 33 #define CLK_TOP_MUX_SCP 34 #define CLK_TOP_MUX_ATB 35 #define CLK_TOP_MUX_MJC 36 #define CLK_TOP_MUX_DPI0 37 #define CLK_TOP_MUX_AUD_1 38 #define CLK_TOP_MUX_AUD_2 39 #define CLK_TOP_MUX_SSUSB_TOP_SYS 40 #define CLK_TOP_MUX_SPM 41 #define CLK_TOP_MUX_BSI_SPI 42 #define CLK_TOP_MUX_AUDIO_H 43 #define CLK_TOP_MUX_ANC_MD32 44 #define CLK_TOP_MUX_MFG_52M 45 #define CLK_TOP_SYSPLL_CK 46 #define CLK_TOP_SYSPLL_D2 47 #define CLK_TOP_SYSPLL1_D2 48 #define CLK_TOP_SYSPLL1_D4 49 #define CLK_TOP_SYSPLL1_D8 50 #define CLK_TOP_SYSPLL1_D16 51 #define CLK_TOP_SYSPLL_D3 52 #define CLK_TOP_SYSPLL_D3_D3 53 #define CLK_TOP_SYSPLL2_D2 54 #define CLK_TOP_SYSPLL2_D4 55 #define CLK_TOP_SYSPLL2_D8 56 #define CLK_TOP_SYSPLL_D5 57 #define CLK_TOP_SYSPLL3_D2 58 #define CLK_TOP_SYSPLL3_D4 59 #define CLK_TOP_SYSPLL_D7 60 #define CLK_TOP_SYSPLL4_D2 61 #define CLK_TOP_SYSPLL4_D4 62 #define CLK_TOP_UNIVPLL_CK 63 #define CLK_TOP_UNIVPLL_D7 64 #define CLK_TOP_UNIVPLL_D26 65 #define CLK_TOP_SSUSB_PHY_48M_CK 66 #define CLK_TOP_USB_PHY48M_CK 67 #define CLK_TOP_UNIVPLL_D2 68 #define CLK_TOP_UNIVPLL1_D2 69 #define CLK_TOP_UNIVPLL1_D4 70 #define CLK_TOP_UNIVPLL1_D8 71 #define CLK_TOP_UNIVPLL_D3 72 #define CLK_TOP_UNIVPLL2_D2 73 #define CLK_TOP_UNIVPLL2_D4 74 #define CLK_TOP_UNIVPLL2_D8 75 #define CLK_TOP_UNIVPLL_D5 76 #define CLK_TOP_UNIVPLL3_D2 77 #define CLK_TOP_UNIVPLL3_D4 78 #define CLK_TOP_UNIVPLL3_D8 79 #define CLK_TOP_ULPOSC_CK_ORG 80 #define CLK_TOP_ULPOSC_CK 81 #define CLK_TOP_ULPOSC_D2 82 #define CLK_TOP_ULPOSC_D3 83 #define CLK_TOP_ULPOSC_D4 84 #define CLK_TOP_ULPOSC_D8 85 #define CLK_TOP_ULPOSC_D10 86 #define CLK_TOP_APLL1_CK 87 #define CLK_TOP_APLL2_CK 88 #define CLK_TOP_MFGPLL_CK 89 #define CLK_TOP_MFGPLL_D2 90 #define CLK_TOP_IMGPLL_CK 91 #define CLK_TOP_IMGPLL_D2 92 #define CLK_TOP_IMGPLL_D4 93 #define CLK_TOP_CODECPLL_CK 94 #define CLK_TOP_CODECPLL_D2 95 #define CLK_TOP_VDECPLL_CK 96 #define CLK_TOP_TVDPLL_CK 97 #define CLK_TOP_TVDPLL_D2 98 #define CLK_TOP_TVDPLL_D4 99 #define CLK_TOP_TVDPLL_D8 100 #define CLK_TOP_TVDPLL_D16 101 #define CLK_TOP_MSDCPLL_CK 102 #define CLK_TOP_MSDCPLL_D2 103 #define CLK_TOP_MSDCPLL_D4 104 #define CLK_TOP_MSDCPLL_D8 105 #define CLK_TOP_NR 106 107 /* APMIXED_SYS */ 108 #define CLK_APMIXED_MAINPLL 109 #define CLK_APMIXED_UNIVPLL 110 #define CLK_APMIXED_MFGPLL 111 #define CLK_APMIXED_MSDCPLL 112 #define CLK_APMIXED_IMGPLL 113 #define CLK_APMIXED_TVDPLL 114 #define CLK_APMIXED_CODECPLL 115 #define CLK_APMIXED_VDECPLL 116 #define CLK_APMIXED_APLL1 117 #define CLK_APMIXED_APLL2 118 #define CLK_APMIXED_NR 119 120 /* INFRA_SYS */ 121 #define CLK_INFRA_PMIC_TMR 122 #define CLK_INFRA_PMIC_AP 123 #define CLK_INFRA_PMIC_MD 124 #define CLK_INFRA_PMIC_CONN 125 #define CLK_INFRA_SCP 126 #define CLK_INFRA_SEJ 127 #define CLK_INFRA_APXGPT 128 #define CLK_INFRA_SEJ_13M 129 #define CLK_INFRA_ICUSB 130 #define CLK_INFRA_GCE 131 #define CLK_INFRA_THERM 132 #define CLK_INFRA_I2C0 133 #define CLK_INFRA_I2C1 134 #define CLK_INFRA_I2C2 135 #define CLK_INFRA_I2C3 136 #define CLK_INFRA_PWM_HCLK 137 #define CLK_INFRA_PWM1 138 #define CLK_INFRA_PWM2 139 #define CLK_INFRA_PWM3 140 #define CLK_INFRA_PWM4 141 #define CLK_INFRA_PWM 142 #define CLK_INFRA_UART0 143 #define CLK_INFRA_UART1 144 #define CLK_INFRA_UART2 145 #define CLK_INFRA_UART3 146 #define CLK_INFRA_MD2MD_CCIF_0 147 #define CLK_INFRA_MD2MD_CCIF_1 148 #define CLK_INFRA_MD2MD_CCIF_2 149 #define CLK_INFRA_FHCTL 150 #define CLK_INFRA_BTIF 151 #define CLK_INFRA_MD2MD_CCIF_3 152 #define CLK_INFRA_SPI 153 #define CLK_INFRA_MSDC0 154 #define CLK_INFRA_MD2MD_CCIF_4 155 #define CLK_INFRA_MSDC1 156 #define CLK_INFRA_MSDC2 157 #define CLK_INFRA_MD2MD_CCIF_5 158 #define CLK_INFRA_GCPU 159 #define CLK_INFRA_TRNG 160 #define CLK_INFRA_AUXADC 161 #define CLK_INFRA_CPUM 162 #define CLK_INFRA_AP_C2K_CCIF_0 163 #define CLK_INFRA_AP_C2K_CCIF_1 164 #define CLK_INFRA_CLDMA 165 #define CLK_INFRA_DISP_PWM 166 #define CLK_INFRA_AP_DMA 167 #define CLK_INFRA_DEVICE_APC 168 #define CLK_INFRA_L2C_SRAM 169 #define CLK_INFRA_CCIF_AP 170 #define CLK_INFRA_AUDIO 171 #define CLK_INFRA_CCIF_MD 172 #define CLK_INFRA_DRAMC_F26M 173 #define CLK_INFRA_I2C4 174 #define CLK_INFRA_I2C_APPM 175 #define CLK_INFRA_I2C_GPUPM 176 #define CLK_INFRA_I2C2_IMM 177 #define CLK_INFRA_I2C2_ARB 178 #define CLK_INFRA_I2C3_IMM 179 #define CLK_INFRA_I2C3_ARB 180 #define CLK_INFRA_I2C5 181 #define CLK_INFRA_SYS_CIRQ 182 #define CLK_INFRA_SPI1 183 #define CLK_INFRA_DRAMC_B_F26M 184 #define CLK_INFRA_ANC_MD32 185 #define CLK_INFRA_ANC_MD32_32K 186 #define CLK_INFRA_DVFS_SPM1 187 #define CLK_INFRA_AES_TOP0 188 #define CLK_INFRA_AES_TOP1 189 #define CLK_INFRA_SSUSB_BUS 190 #define CLK_INFRA_SPI2 191 #define CLK_INFRA_SPI3 192 #define CLK_INFRA_SPI4 193 #define CLK_INFRA_SPI5 194 #define CLK_INFRA_IRTX 195 #define CLK_INFRA_SSUSB_SYS 196 #define CLK_INFRA_SSUSB_REF 197 #define CLK_INFRA_AUDIO_26M 198 #define CLK_INFRA_AUDIO_26M_PAD_TOP 199 #define CLK_INFRA_MODEM_TEMP_SHARE 200 #define CLK_INFRA_VAD_WRAP_SOC 201 #define CLK_INFRA_DRAMC_CONF 202 #define CLK_INFRA_DRAMC_B_CONF 203 #define CLK_INFRA_MFG_VCG 204 #define CLK_INFRA_13M 205 #define CLK_INFRA_NR 206 207 /* IMG_SYS */ 208 #define CLK_IMG_FDVT 209 #define CLK_IMG_DPE 210 #define CLK_IMG_DIP 211 #define CLK_IMG_LARB6 212 #define CLK_IMG_NR 213 214 /* MM_SYS */ 215 #define CLK_MM_SMI_COMMON 216 #define CLK_MM_SMI_LARB0 217 #define CLK_MM_SMI_LARB5 218 #define CLK_MM_CAM_MDP 219 #define CLK_MM_MDP_RDMA0 220 #define CLK_MM_MDP_RDMA1 221 #define CLK_MM_MDP_RSZ0 222 #define CLK_MM_MDP_RSZ1 223 #define CLK_MM_MDP_RSZ2 224 #define CLK_MM_MDP_TDSHP 225 #define CLK_MM_MDP_COLOR 226 #define CLK_MM_MDP_WDMA 227 #define CLK_MM_MDP_WROT0 228 #define CLK_MM_MDP_WROT1 229 #define CLK_MM_FAKE_ENG 230 #define CLK_MM_DISP_OVL0 231 #define CLK_MM_DISP_OVL1 232 #define CLK_MM_DISP_OVL0_2L 233 #define CLK_MM_DISP_OVL1_2L 234 #define CLK_MM_DISP_RDMA0 235 #define CLK_MM_DISP_RDMA1 236 #define CLK_MM_DISP_WDMA0 237 #define CLK_MM_DISP_WDMA1 238 #define CLK_MM_DISP_COLOR 239 #define CLK_MM_DISP_CCORR 240 #define CLK_MM_DISP_AAL 241 #define CLK_MM_DISP_GAMMA 242 #define CLK_MM_DISP_OD 243 #define CLK_MM_DISP_DITHER 244 #define CLK_MM_DISP_UFOE 245 #define CLK_MM_DISP_DSC 246 #define CLK_MM_DISP_SPLIT 247 #define CLK_MM_DSI0_MM_CLOCK 248 #define CLK_MM_DSI1_MM_CLOCK 249 #define CLK_MM_DPI_MM_CLOCK 250 #define CLK_MM_DPI_INTERFACE_CLOCK 251 #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 252 #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 253 #define CLK_MM_DISP_OVL0_MOUT_CLOCK 254 #define CLK_MM_FAKE_ENG2 255 #define CLK_MM_DSI0_INTERFACE_CLOCK 256 #define CLK_MM_DSI1_INTERFACE_CLOCK 257 #define CLK_MM_NR 258 259 /* VDEC_SYS */ 260 #define CLK_VDEC_CKEN_ENG 261 #define CLK_VDEC_ACTIVE 262 #define CLK_VDEC_CKEN 263 #define CLK_VDEC_LARB1_CKEN 264 #define CLK_VDEC_NR 265 266 /* VENC_SYS */ 267 #define CLK_VENC_0 268 #define CLK_VENC_1 269 #define CLK_VENC_2 270 #define CLK_VENC_3 271 #define CLK_VENC_NR 272 273 #endif /* _DT_BINDINGS_CLK_MT6797_H */ 274
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