1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (c) 2014 MediaTek Inc. 2 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.c 3 * Author: James Liao <jamesjj.liao@mediatek.com>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License version 2 as
>> 7 * published by the Free Software Foundation.
>> 8 *
>> 9 * This program is distributed in the hope that it will be useful,
>> 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 12 * GNU General Public License for more details.
5 */ 13 */
6 14
7 #ifndef _DT_BINDINGS_CLK_MT8135_H 15 #ifndef _DT_BINDINGS_CLK_MT8135_H
8 #define _DT_BINDINGS_CLK_MT8135_H 16 #define _DT_BINDINGS_CLK_MT8135_H
9 17
10 /* TOPCKGEN */ 18 /* TOPCKGEN */
11 19
12 #define CLK_TOP_DSI0_LNTC_DSICLK 1 20 #define CLK_TOP_DSI0_LNTC_DSICLK 1
13 #define CLK_TOP_HDMITX_CLKDIG_CTS 2 21 #define CLK_TOP_HDMITX_CLKDIG_CTS 2
14 #define CLK_TOP_CLKPH_MCK 3 22 #define CLK_TOP_CLKPH_MCK 3
15 #define CLK_TOP_CPUM_TCK_IN 4 23 #define CLK_TOP_CPUM_TCK_IN 4
16 #define CLK_TOP_MAINPLL_806M 5 24 #define CLK_TOP_MAINPLL_806M 5
17 #define CLK_TOP_MAINPLL_537P3M 6 25 #define CLK_TOP_MAINPLL_537P3M 6
18 #define CLK_TOP_MAINPLL_322P4M 7 26 #define CLK_TOP_MAINPLL_322P4M 7
19 #define CLK_TOP_MAINPLL_230P3M 8 27 #define CLK_TOP_MAINPLL_230P3M 8
20 #define CLK_TOP_UNIVPLL_624M 9 28 #define CLK_TOP_UNIVPLL_624M 9
21 #define CLK_TOP_UNIVPLL_416M 10 29 #define CLK_TOP_UNIVPLL_416M 10
22 #define CLK_TOP_UNIVPLL_249P6M 11 30 #define CLK_TOP_UNIVPLL_249P6M 11
23 #define CLK_TOP_UNIVPLL_178P3M 12 31 #define CLK_TOP_UNIVPLL_178P3M 12
24 #define CLK_TOP_UNIVPLL_48M 13 32 #define CLK_TOP_UNIVPLL_48M 13
25 #define CLK_TOP_MMPLL_D2 14 33 #define CLK_TOP_MMPLL_D2 14
26 #define CLK_TOP_MMPLL_D3 15 34 #define CLK_TOP_MMPLL_D3 15
27 #define CLK_TOP_MMPLL_D5 16 35 #define CLK_TOP_MMPLL_D5 16
28 #define CLK_TOP_MMPLL_D7 17 36 #define CLK_TOP_MMPLL_D7 17
29 #define CLK_TOP_MMPLL_D4 18 37 #define CLK_TOP_MMPLL_D4 18
30 #define CLK_TOP_MMPLL_D6 19 38 #define CLK_TOP_MMPLL_D6 19
31 #define CLK_TOP_SYSPLL_D2 20 39 #define CLK_TOP_SYSPLL_D2 20
32 #define CLK_TOP_SYSPLL_D4 21 40 #define CLK_TOP_SYSPLL_D4 21
33 #define CLK_TOP_SYSPLL_D6 22 41 #define CLK_TOP_SYSPLL_D6 22
34 #define CLK_TOP_SYSPLL_D8 23 42 #define CLK_TOP_SYSPLL_D8 23
35 #define CLK_TOP_SYSPLL_D10 24 43 #define CLK_TOP_SYSPLL_D10 24
36 #define CLK_TOP_SYSPLL_D12 25 44 #define CLK_TOP_SYSPLL_D12 25
37 #define CLK_TOP_SYSPLL_D16 26 45 #define CLK_TOP_SYSPLL_D16 26
38 #define CLK_TOP_SYSPLL_D24 27 46 #define CLK_TOP_SYSPLL_D24 27
39 #define CLK_TOP_SYSPLL_D3 28 47 #define CLK_TOP_SYSPLL_D3 28
40 #define CLK_TOP_SYSPLL_D2P5 29 48 #define CLK_TOP_SYSPLL_D2P5 29
41 #define CLK_TOP_SYSPLL_D5 30 49 #define CLK_TOP_SYSPLL_D5 30
42 #define CLK_TOP_SYSPLL_D3P5 31 50 #define CLK_TOP_SYSPLL_D3P5 31
43 #define CLK_TOP_UNIVPLL1_D2 32 51 #define CLK_TOP_UNIVPLL1_D2 32
44 #define CLK_TOP_UNIVPLL1_D4 33 52 #define CLK_TOP_UNIVPLL1_D4 33
45 #define CLK_TOP_UNIVPLL1_D6 34 53 #define CLK_TOP_UNIVPLL1_D6 34
46 #define CLK_TOP_UNIVPLL1_D8 35 54 #define CLK_TOP_UNIVPLL1_D8 35
47 #define CLK_TOP_UNIVPLL1_D10 36 55 #define CLK_TOP_UNIVPLL1_D10 36
48 #define CLK_TOP_UNIVPLL2_D2 37 56 #define CLK_TOP_UNIVPLL2_D2 37
49 #define CLK_TOP_UNIVPLL2_D4 38 57 #define CLK_TOP_UNIVPLL2_D4 38
50 #define CLK_TOP_UNIVPLL2_D6 39 58 #define CLK_TOP_UNIVPLL2_D6 39
51 #define CLK_TOP_UNIVPLL2_D8 40 59 #define CLK_TOP_UNIVPLL2_D8 40
52 #define CLK_TOP_UNIVPLL_D3 41 60 #define CLK_TOP_UNIVPLL_D3 41
53 #define CLK_TOP_UNIVPLL_D5 42 61 #define CLK_TOP_UNIVPLL_D5 42
54 #define CLK_TOP_UNIVPLL_D7 43 62 #define CLK_TOP_UNIVPLL_D7 43
55 #define CLK_TOP_UNIVPLL_D10 44 63 #define CLK_TOP_UNIVPLL_D10 44
56 #define CLK_TOP_UNIVPLL_D26 45 64 #define CLK_TOP_UNIVPLL_D26 45
57 #define CLK_TOP_APLL 46 65 #define CLK_TOP_APLL 46
58 #define CLK_TOP_APLL_D4 47 66 #define CLK_TOP_APLL_D4 47
59 #define CLK_TOP_APLL_D8 48 67 #define CLK_TOP_APLL_D8 48
60 #define CLK_TOP_APLL_D16 49 68 #define CLK_TOP_APLL_D16 49
61 #define CLK_TOP_APLL_D24 50 69 #define CLK_TOP_APLL_D24 50
62 #define CLK_TOP_LVDSPLL_D2 51 70 #define CLK_TOP_LVDSPLL_D2 51
63 #define CLK_TOP_LVDSPLL_D4 52 71 #define CLK_TOP_LVDSPLL_D4 52
64 #define CLK_TOP_LVDSPLL_D8 53 72 #define CLK_TOP_LVDSPLL_D8 53
65 #define CLK_TOP_LVDSTX_CLKDIG_CT 54 73 #define CLK_TOP_LVDSTX_CLKDIG_CT 54
66 #define CLK_TOP_VPLL_DPIX 55 74 #define CLK_TOP_VPLL_DPIX 55
67 #define CLK_TOP_TVHDMI_H 56 75 #define CLK_TOP_TVHDMI_H 56
68 #define CLK_TOP_HDMITX_CLKDIG_D2 57 76 #define CLK_TOP_HDMITX_CLKDIG_D2 57
69 #define CLK_TOP_HDMITX_CLKDIG_D3 58 77 #define CLK_TOP_HDMITX_CLKDIG_D3 58
70 #define CLK_TOP_TVHDMI_D2 59 78 #define CLK_TOP_TVHDMI_D2 59
71 #define CLK_TOP_TVHDMI_D4 60 79 #define CLK_TOP_TVHDMI_D4 60
72 #define CLK_TOP_MEMPLL_MCK_D4 61 80 #define CLK_TOP_MEMPLL_MCK_D4 61
73 #define CLK_TOP_AXI_SEL 62 81 #define CLK_TOP_AXI_SEL 62
74 #define CLK_TOP_SMI_SEL 63 82 #define CLK_TOP_SMI_SEL 63
75 #define CLK_TOP_MFG_SEL 64 83 #define CLK_TOP_MFG_SEL 64
76 #define CLK_TOP_IRDA_SEL 65 84 #define CLK_TOP_IRDA_SEL 65
77 #define CLK_TOP_CAM_SEL 66 85 #define CLK_TOP_CAM_SEL 66
78 #define CLK_TOP_AUD_INTBUS_SEL 67 86 #define CLK_TOP_AUD_INTBUS_SEL 67
79 #define CLK_TOP_JPG_SEL 68 87 #define CLK_TOP_JPG_SEL 68
80 #define CLK_TOP_DISP_SEL 69 88 #define CLK_TOP_DISP_SEL 69
81 #define CLK_TOP_MSDC30_1_SEL 70 89 #define CLK_TOP_MSDC30_1_SEL 70
82 #define CLK_TOP_MSDC30_2_SEL 71 90 #define CLK_TOP_MSDC30_2_SEL 71
83 #define CLK_TOP_MSDC30_3_SEL 72 91 #define CLK_TOP_MSDC30_3_SEL 72
84 #define CLK_TOP_MSDC30_4_SEL 73 92 #define CLK_TOP_MSDC30_4_SEL 73
85 #define CLK_TOP_USB20_SEL 74 93 #define CLK_TOP_USB20_SEL 74
86 #define CLK_TOP_VENC_SEL 75 94 #define CLK_TOP_VENC_SEL 75
87 #define CLK_TOP_SPI_SEL 76 95 #define CLK_TOP_SPI_SEL 76
88 #define CLK_TOP_UART_SEL 77 96 #define CLK_TOP_UART_SEL 77
89 #define CLK_TOP_MEM_SEL 78 97 #define CLK_TOP_MEM_SEL 78
90 #define CLK_TOP_CAMTG_SEL 79 98 #define CLK_TOP_CAMTG_SEL 79
91 #define CLK_TOP_AUDIO_SEL 80 99 #define CLK_TOP_AUDIO_SEL 80
92 #define CLK_TOP_FIX_SEL 81 100 #define CLK_TOP_FIX_SEL 81
93 #define CLK_TOP_VDEC_SEL 82 101 #define CLK_TOP_VDEC_SEL 82
94 #define CLK_TOP_DDRPHYCFG_SEL 83 102 #define CLK_TOP_DDRPHYCFG_SEL 83
95 #define CLK_TOP_DPILVDS_SEL 84 103 #define CLK_TOP_DPILVDS_SEL 84
96 #define CLK_TOP_PMICSPI_SEL 85 104 #define CLK_TOP_PMICSPI_SEL 85
97 #define CLK_TOP_MSDC30_0_SEL 86 105 #define CLK_TOP_MSDC30_0_SEL 86
98 #define CLK_TOP_SMI_MFG_AS_SEL 87 106 #define CLK_TOP_SMI_MFG_AS_SEL 87
99 #define CLK_TOP_GCPU_SEL 88 107 #define CLK_TOP_GCPU_SEL 88
100 #define CLK_TOP_DPI1_SEL 89 108 #define CLK_TOP_DPI1_SEL 89
101 #define CLK_TOP_CCI_SEL 90 109 #define CLK_TOP_CCI_SEL 90
102 #define CLK_TOP_APLL_SEL 91 110 #define CLK_TOP_APLL_SEL 91
103 #define CLK_TOP_HDMIPLL_SEL 92 111 #define CLK_TOP_HDMIPLL_SEL 92
104 #define CLK_TOP_NR_CLK 93 112 #define CLK_TOP_NR_CLK 93
105 113
106 /* APMIXED_SYS */ 114 /* APMIXED_SYS */
107 115
108 #define CLK_APMIXED_ARMPLL1 1 116 #define CLK_APMIXED_ARMPLL1 1
109 #define CLK_APMIXED_ARMPLL2 2 117 #define CLK_APMIXED_ARMPLL2 2
110 #define CLK_APMIXED_MAINPLL 3 118 #define CLK_APMIXED_MAINPLL 3
111 #define CLK_APMIXED_UNIVPLL 4 119 #define CLK_APMIXED_UNIVPLL 4
112 #define CLK_APMIXED_MMPLL 5 120 #define CLK_APMIXED_MMPLL 5
113 #define CLK_APMIXED_MSDCPLL 6 121 #define CLK_APMIXED_MSDCPLL 6
114 #define CLK_APMIXED_TVDPLL 7 122 #define CLK_APMIXED_TVDPLL 7
115 #define CLK_APMIXED_LVDSPLL 8 123 #define CLK_APMIXED_LVDSPLL 8
116 #define CLK_APMIXED_AUDPLL 9 124 #define CLK_APMIXED_AUDPLL 9
117 #define CLK_APMIXED_VDECPLL 10 125 #define CLK_APMIXED_VDECPLL 10
118 #define CLK_APMIXED_NR_CLK 11 126 #define CLK_APMIXED_NR_CLK 11
119 127
120 /* INFRA_SYS */ 128 /* INFRA_SYS */
121 129
122 #define CLK_INFRA_PMIC_WRAP 1 130 #define CLK_INFRA_PMIC_WRAP 1
123 #define CLK_INFRA_PMICSPI 2 131 #define CLK_INFRA_PMICSPI 2
124 #define CLK_INFRA_CCIF1_AP_CTRL 3 132 #define CLK_INFRA_CCIF1_AP_CTRL 3
125 #define CLK_INFRA_CCIF0_AP_CTRL 4 133 #define CLK_INFRA_CCIF0_AP_CTRL 4
126 #define CLK_INFRA_KP 5 134 #define CLK_INFRA_KP 5
127 #define CLK_INFRA_CPUM 6 135 #define CLK_INFRA_CPUM 6
128 #define CLK_INFRA_M4U 7 136 #define CLK_INFRA_M4U 7
129 #define CLK_INFRA_MFGAXI 8 137 #define CLK_INFRA_MFGAXI 8
130 #define CLK_INFRA_DEVAPC 9 138 #define CLK_INFRA_DEVAPC 9
131 #define CLK_INFRA_AUDIO 10 139 #define CLK_INFRA_AUDIO 10
132 #define CLK_INFRA_MFG_BUS 11 140 #define CLK_INFRA_MFG_BUS 11
133 #define CLK_INFRA_SMI 12 141 #define CLK_INFRA_SMI 12
134 #define CLK_INFRA_DBGCLK 13 142 #define CLK_INFRA_DBGCLK 13
135 #define CLK_INFRA_NR_CLK 14 143 #define CLK_INFRA_NR_CLK 14
136 144
137 /* PERI_SYS */ 145 /* PERI_SYS */
138 146
139 #define CLK_PERI_I2C5 1 147 #define CLK_PERI_I2C5 1
140 #define CLK_PERI_I2C4 2 148 #define CLK_PERI_I2C4 2
141 #define CLK_PERI_I2C3 3 149 #define CLK_PERI_I2C3 3
142 #define CLK_PERI_I2C2 4 150 #define CLK_PERI_I2C2 4
143 #define CLK_PERI_I2C1 5 151 #define CLK_PERI_I2C1 5
144 #define CLK_PERI_I2C0 6 152 #define CLK_PERI_I2C0 6
145 #define CLK_PERI_UART3 7 153 #define CLK_PERI_UART3 7
146 #define CLK_PERI_UART2 8 154 #define CLK_PERI_UART2 8
147 #define CLK_PERI_UART1 9 155 #define CLK_PERI_UART1 9
148 #define CLK_PERI_UART0 10 156 #define CLK_PERI_UART0 10
149 #define CLK_PERI_IRDA 11 157 #define CLK_PERI_IRDA 11
150 #define CLK_PERI_NLI 12 158 #define CLK_PERI_NLI 12
151 #define CLK_PERI_MD_HIF 13 159 #define CLK_PERI_MD_HIF 13
152 #define CLK_PERI_AP_HIF 14 160 #define CLK_PERI_AP_HIF 14
153 #define CLK_PERI_MSDC30_3 15 161 #define CLK_PERI_MSDC30_3 15
154 #define CLK_PERI_MSDC30_2 16 162 #define CLK_PERI_MSDC30_2 16
155 #define CLK_PERI_MSDC30_1 17 163 #define CLK_PERI_MSDC30_1 17
156 #define CLK_PERI_MSDC20_2 18 164 #define CLK_PERI_MSDC20_2 18
157 #define CLK_PERI_MSDC20_1 19 165 #define CLK_PERI_MSDC20_1 19
158 #define CLK_PERI_AP_DMA 20 166 #define CLK_PERI_AP_DMA 20
159 #define CLK_PERI_USB1 21 167 #define CLK_PERI_USB1 21
160 #define CLK_PERI_USB0 22 168 #define CLK_PERI_USB0 22
161 #define CLK_PERI_PWM 23 169 #define CLK_PERI_PWM 23
162 #define CLK_PERI_PWM7 24 170 #define CLK_PERI_PWM7 24
163 #define CLK_PERI_PWM6 25 171 #define CLK_PERI_PWM6 25
164 #define CLK_PERI_PWM5 26 172 #define CLK_PERI_PWM5 26
165 #define CLK_PERI_PWM4 27 173 #define CLK_PERI_PWM4 27
166 #define CLK_PERI_PWM3 28 174 #define CLK_PERI_PWM3 28
167 #define CLK_PERI_PWM2 29 175 #define CLK_PERI_PWM2 29
168 #define CLK_PERI_PWM1 30 176 #define CLK_PERI_PWM1 30
169 #define CLK_PERI_THERM 31 177 #define CLK_PERI_THERM 31
170 #define CLK_PERI_NFI 32 178 #define CLK_PERI_NFI 32
171 #define CLK_PERI_USBSLV 33 179 #define CLK_PERI_USBSLV 33
172 #define CLK_PERI_USB1_MCU 34 180 #define CLK_PERI_USB1_MCU 34
173 #define CLK_PERI_USB0_MCU 35 181 #define CLK_PERI_USB0_MCU 35
174 #define CLK_PERI_GCPU 36 182 #define CLK_PERI_GCPU 36
175 #define CLK_PERI_FHCTL 37 183 #define CLK_PERI_FHCTL 37
176 #define CLK_PERI_SPI1 38 184 #define CLK_PERI_SPI1 38
177 #define CLK_PERI_AUXADC 39 185 #define CLK_PERI_AUXADC 39
178 #define CLK_PERI_PERI_PWRAP 40 186 #define CLK_PERI_PERI_PWRAP 40
179 #define CLK_PERI_I2C6 41 187 #define CLK_PERI_I2C6 41
180 #define CLK_PERI_UART0_SEL 42 188 #define CLK_PERI_UART0_SEL 42
181 #define CLK_PERI_UART1_SEL 43 189 #define CLK_PERI_UART1_SEL 43
182 #define CLK_PERI_UART2_SEL 44 190 #define CLK_PERI_UART2_SEL 44
183 #define CLK_PERI_UART3_SEL 45 191 #define CLK_PERI_UART3_SEL 45
184 #define CLK_PERI_NR_CLK 46 192 #define CLK_PERI_NR_CLK 46
185 193
186 #endif /* _DT_BINDINGS_CLK_MT8135_H */ 194 #endif /* _DT_BINDINGS_CLK_MT8135_H */
187 195
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