1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright 2017 Texas Instruments, Inc. 2 * Copyright 2017 Texas Instruments, Inc.
>> 3 *
>> 4 * This software is licensed under the terms of the GNU General Public
>> 5 * License version 2, as published by the Free Software Foundation, and
>> 6 * may be copied, distributed, and modified under those terms.
>> 7 *
>> 8 * This program is distributed in the hope that it will be useful,
>> 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 11 * GNU General Public License for more details.
4 */ 12 */
5 #ifndef __DT_BINDINGS_CLK_OMAP4_H 13 #ifndef __DT_BINDINGS_CLK_OMAP4_H
6 #define __DT_BINDINGS_CLK_OMAP4_H 14 #define __DT_BINDINGS_CLK_OMAP4_H
7 15
8 #define OMAP4_CLKCTRL_OFFSET 0x20 16 #define OMAP4_CLKCTRL_OFFSET 0x20
9 #define OMAP4_CLKCTRL_INDEX(offset) ((offs 17 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
10 18
11 /* mpuss clocks */ 19 /* mpuss clocks */
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_ 20 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
13 21
14 /* tesla clocks */ 22 /* tesla clocks */
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_ 23 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
16 24
17 /* abe clocks */ 25 /* abe clocks */
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_ 26 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_ 27 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_ 28 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_ 29 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_ 30 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_ 31 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_ 32 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
25 #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_ 33 #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
26 #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_ 34 #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
27 #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_ 35 #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
28 #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_ 36 #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
29 #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_ 37 #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
30 #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_ 38 #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
31 #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_ 39 #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
32 40
33 /* l4_ao clocks */ 41 /* l4_ao clocks */
34 #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_ 42 #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
35 #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_ 43 #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
36 #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_ 44 #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
37 45
38 /* l3_1 clocks */ 46 /* l3_1 clocks */
39 #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_ 47 #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
40 48
41 /* l3_2 clocks */ 49 /* l3_2 clocks */
42 #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_ 50 #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
43 #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_ 51 #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
44 #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_ 52 #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
45 53
46 /* ducati clocks */ 54 /* ducati clocks */
47 #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_ 55 #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
48 56
49 /* l3_dma clocks */ 57 /* l3_dma clocks */
50 #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_ 58 #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
51 59
52 /* l3_emif clocks */ 60 /* l3_emif clocks */
53 #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_ 61 #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
54 #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_ 62 #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
55 #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_ 63 #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
56 64
57 /* d2d clocks */ 65 /* d2d clocks */
58 #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_ 66 #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
59 67
60 /* l4_cfg clocks */ 68 /* l4_cfg clocks */
61 #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_ 69 #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
62 #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_ 70 #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
63 #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_ 71 #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
64 72
65 /* l3_instr clocks */ 73 /* l3_instr clocks */
66 #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_ 74 #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
67 #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_ 75 #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
68 #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_ 76 #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
69 77
70 /* ivahd clocks */ 78 /* ivahd clocks */
71 #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_ 79 #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
72 #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_ 80 #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
73 81
74 /* iss clocks */ 82 /* iss clocks */
75 #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_ 83 #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
76 #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_ 84 #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
77 85
78 /* l3_dss clocks */ 86 /* l3_dss clocks */
79 #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_ 87 #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
80 88
81 /* l3_gfx clocks */ 89 /* l3_gfx clocks */
82 #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_ 90 #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
83 91
84 /* l3_init clocks */ 92 /* l3_init clocks */
85 #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_ 93 #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
86 #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_ 94 #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
87 #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_ 95 #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
88 #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_ 96 #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
89 #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_ 97 #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
90 #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_ 98 #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
91 #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_ 99 #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
92 #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_ 100 #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
93 101
94 /* l4_per clocks */ 102 /* l4_per clocks */
95 #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_ 103 #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
96 #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_ 104 #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
97 #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_ 105 #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
98 #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_ 106 #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
99 #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_ 107 #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
100 #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_ 108 #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
101 #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_ 109 #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
102 #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_ 110 #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
103 #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_ 111 #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
104 #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_ 112 #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
105 #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_ 113 #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
106 #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_ 114 #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
107 #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_ 115 #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
108 #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_ 116 #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
109 #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_ 117 #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
110 #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_ 118 #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
111 #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_ 119 #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
112 #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_ 120 #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
113 #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_ 121 #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
114 #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_ 122 #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
115 #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_ 123 #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
116 #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_ 124 #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
117 #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_ 125 #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
118 #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_ 126 #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
119 #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_ 127 #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
120 #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_ 128 #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
121 #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_ 129 #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
122 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_ 130 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
123 #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_ 131 #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
124 #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_ 132 #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
125 #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_ 133 #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
126 <<
127 /* l4_secure clocks */ <<
128 #define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 <<
129 #define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) <<
130 #define OMAP4_AES1_CLKCTRL OMAP4_L4_SECUR <<
131 #define OMAP4_AES2_CLKCTRL OMAP4_L4_SECUR <<
132 #define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECUR <<
133 #define OMAP4_PKA_CLKCTRL OMAP4_L4_SECUR <<
134 #define OMAP4_RNG_CLKCTRL OMAP4_L4_SECUR <<
135 #define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECUR <<
136 #define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECUR <<
137 134
138 /* l4_wkup clocks */ 135 /* l4_wkup clocks */
139 #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_ 136 #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
140 #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_ 137 #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
141 #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_ 138 #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
142 #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_ 139 #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
143 #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_ 140 #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
144 #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_ 141 #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
145 142
146 /* emu_sys clocks */ 143 /* emu_sys clocks */
147 #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_ 144 #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
148 145
149 #endif 146 #endif
150 147
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