1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2014 Google, Inc. 2 * Copyright (C) 2014 Google, Inc.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify it
>> 5 * under the terms and conditions of the GNU General Public License,
>> 6 * version 2, as published by the Free Software Foundation.
4 */ 7 */
5 8
6 #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H 9 #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
7 #define _DT_BINDINGS_CLOCK_PISTACHIO_H 10 #define _DT_BINDINGS_CLOCK_PISTACHIO_H
8 11
9 /* PLLs */ 12 /* PLLs */
10 #define CLK_MIPS_PLL 0 13 #define CLK_MIPS_PLL 0
11 #define CLK_AUDIO_PLL 1 14 #define CLK_AUDIO_PLL 1
12 #define CLK_RPU_V_PLL 2 15 #define CLK_RPU_V_PLL 2
13 #define CLK_RPU_L_PLL 3 16 #define CLK_RPU_L_PLL 3
14 #define CLK_SYS_PLL 4 17 #define CLK_SYS_PLL 4
15 #define CLK_WIFI_PLL 5 18 #define CLK_WIFI_PLL 5
16 #define CLK_BT_PLL 6 19 #define CLK_BT_PLL 6
17 20
18 /* Fixed-factor clocks */ 21 /* Fixed-factor clocks */
19 #define CLK_WIFI_DIV4 16 22 #define CLK_WIFI_DIV4 16
20 #define CLK_WIFI_DIV8 17 23 #define CLK_WIFI_DIV8 17
21 24
22 /* Gate clocks */ 25 /* Gate clocks */
23 #define CLK_MIPS 32 26 #define CLK_MIPS 32
24 #define CLK_AUDIO_IN 33 27 #define CLK_AUDIO_IN 33
25 #define CLK_AUDIO 34 28 #define CLK_AUDIO 34
26 #define CLK_I2S 35 29 #define CLK_I2S 35
27 #define CLK_SPDIF 36 30 #define CLK_SPDIF 36
28 #define CLK_AUDIO_DAC 37 31 #define CLK_AUDIO_DAC 37
29 #define CLK_RPU_V 38 32 #define CLK_RPU_V 38
30 #define CLK_RPU_L 39 33 #define CLK_RPU_L 39
31 #define CLK_RPU_SLEEP 40 34 #define CLK_RPU_SLEEP 40
32 #define CLK_WIFI_PLL_GATE 41 35 #define CLK_WIFI_PLL_GATE 41
33 #define CLK_RPU_CORE 42 36 #define CLK_RPU_CORE 42
34 #define CLK_WIFI_ADC 43 37 #define CLK_WIFI_ADC 43
35 #define CLK_WIFI_DAC 44 38 #define CLK_WIFI_DAC 44
36 #define CLK_USB_PHY 45 39 #define CLK_USB_PHY 45
37 #define CLK_ENET_IN 46 40 #define CLK_ENET_IN 46
38 #define CLK_ENET 47 41 #define CLK_ENET 47
39 #define CLK_UART0 48 42 #define CLK_UART0 48
40 #define CLK_UART1 49 43 #define CLK_UART1 49
41 #define CLK_PERIPH_SYS 50 44 #define CLK_PERIPH_SYS 50
42 #define CLK_SPI0 51 45 #define CLK_SPI0 51
43 #define CLK_SPI1 52 46 #define CLK_SPI1 52
44 #define CLK_EVENT_TIMER 53 47 #define CLK_EVENT_TIMER 53
45 #define CLK_AUX_ADC_INTERNAL 54 48 #define CLK_AUX_ADC_INTERNAL 54
46 #define CLK_AUX_ADC 55 49 #define CLK_AUX_ADC 55
47 #define CLK_SD_HOST 56 50 #define CLK_SD_HOST 56
48 #define CLK_BT 57 51 #define CLK_BT 57
49 #define CLK_BT_DIV4 58 52 #define CLK_BT_DIV4 58
50 #define CLK_BT_DIV8 59 53 #define CLK_BT_DIV8 59
51 #define CLK_BT_1MHZ 60 54 #define CLK_BT_1MHZ 60
52 55
53 /* Divider clocks */ 56 /* Divider clocks */
54 #define CLK_MIPS_INTERNAL_DIV 64 57 #define CLK_MIPS_INTERNAL_DIV 64
55 #define CLK_MIPS_DIV 65 58 #define CLK_MIPS_DIV 65
56 #define CLK_AUDIO_DIV 66 59 #define CLK_AUDIO_DIV 66
57 #define CLK_I2S_DIV 67 60 #define CLK_I2S_DIV 67
58 #define CLK_SPDIF_DIV 68 61 #define CLK_SPDIF_DIV 68
59 #define CLK_AUDIO_DAC_DIV 69 62 #define CLK_AUDIO_DAC_DIV 69
60 #define CLK_RPU_V_DIV 70 63 #define CLK_RPU_V_DIV 70
61 #define CLK_RPU_L_DIV 71 64 #define CLK_RPU_L_DIV 71
62 #define CLK_RPU_SLEEP_DIV 72 65 #define CLK_RPU_SLEEP_DIV 72
63 #define CLK_RPU_CORE_DIV 73 66 #define CLK_RPU_CORE_DIV 73
64 #define CLK_USB_PHY_DIV 74 67 #define CLK_USB_PHY_DIV 74
65 #define CLK_ENET_DIV 75 68 #define CLK_ENET_DIV 75
66 #define CLK_UART0_INTERNAL_DIV 76 69 #define CLK_UART0_INTERNAL_DIV 76
67 #define CLK_UART0_DIV 77 70 #define CLK_UART0_DIV 77
68 #define CLK_UART1_INTERNAL_DIV 78 71 #define CLK_UART1_INTERNAL_DIV 78
69 #define CLK_UART1_DIV 79 72 #define CLK_UART1_DIV 79
70 #define CLK_SYS_INTERNAL_DIV 80 73 #define CLK_SYS_INTERNAL_DIV 80
71 #define CLK_SPI0_INTERNAL_DIV 81 74 #define CLK_SPI0_INTERNAL_DIV 81
72 #define CLK_SPI0_DIV 82 75 #define CLK_SPI0_DIV 82
73 #define CLK_SPI1_INTERNAL_DIV 83 76 #define CLK_SPI1_INTERNAL_DIV 83
74 #define CLK_SPI1_DIV 84 77 #define CLK_SPI1_DIV 84
75 #define CLK_EVENT_TIMER_INTERNAL_DIV 85 78 #define CLK_EVENT_TIMER_INTERNAL_DIV 85
76 #define CLK_EVENT_TIMER_DIV 86 79 #define CLK_EVENT_TIMER_DIV 86
77 #define CLK_AUX_ADC_INTERNAL_DIV 87 80 #define CLK_AUX_ADC_INTERNAL_DIV 87
78 #define CLK_AUX_ADC_DIV 88 81 #define CLK_AUX_ADC_DIV 88
79 #define CLK_SD_HOST_DIV 89 82 #define CLK_SD_HOST_DIV 89
80 #define CLK_BT_DIV 90 83 #define CLK_BT_DIV 90
81 #define CLK_BT_DIV4_DIV 91 84 #define CLK_BT_DIV4_DIV 91
82 #define CLK_BT_DIV8_DIV 92 85 #define CLK_BT_DIV8_DIV 92
83 #define CLK_BT_1MHZ_INTERNAL_DIV 93 86 #define CLK_BT_1MHZ_INTERNAL_DIV 93
84 #define CLK_BT_1MHZ_DIV 94 87 #define CLK_BT_1MHZ_DIV 94
85 88
86 /* Mux clocks */ 89 /* Mux clocks */
87 #define CLK_AUDIO_REF_MUX 96 90 #define CLK_AUDIO_REF_MUX 96
88 #define CLK_MIPS_PLL_MUX 97 91 #define CLK_MIPS_PLL_MUX 97
89 #define CLK_AUDIO_PLL_MUX 98 92 #define CLK_AUDIO_PLL_MUX 98
90 #define CLK_AUDIO_MUX 99 93 #define CLK_AUDIO_MUX 99
91 #define CLK_RPU_V_PLL_MUX 100 94 #define CLK_RPU_V_PLL_MUX 100
92 #define CLK_RPU_L_PLL_MUX 101 95 #define CLK_RPU_L_PLL_MUX 101
93 #define CLK_RPU_L_MUX 102 96 #define CLK_RPU_L_MUX 102
94 #define CLK_WIFI_PLL_MUX 103 97 #define CLK_WIFI_PLL_MUX 103
95 #define CLK_WIFI_DIV4_MUX 104 98 #define CLK_WIFI_DIV4_MUX 104
96 #define CLK_WIFI_DIV8_MUX 105 99 #define CLK_WIFI_DIV8_MUX 105
97 #define CLK_RPU_CORE_MUX 106 100 #define CLK_RPU_CORE_MUX 106
98 #define CLK_SYS_PLL_MUX 107 101 #define CLK_SYS_PLL_MUX 107
99 #define CLK_ENET_MUX 108 102 #define CLK_ENET_MUX 108
100 #define CLK_EVENT_TIMER_MUX 109 103 #define CLK_EVENT_TIMER_MUX 109
101 #define CLK_SD_HOST_MUX 110 104 #define CLK_SD_HOST_MUX 110
102 #define CLK_BT_PLL_MUX 111 105 #define CLK_BT_PLL_MUX 111
103 #define CLK_DEBUG_MUX 112 106 #define CLK_DEBUG_MUX 112
104 107
105 #define CLK_NR_CLKS 113 108 #define CLK_NR_CLKS 113
106 109
107 /* Peripheral gate clocks */ 110 /* Peripheral gate clocks */
108 #define PERIPH_CLK_SYS 0 111 #define PERIPH_CLK_SYS 0
109 #define PERIPH_CLK_SYS_BUS 1 112 #define PERIPH_CLK_SYS_BUS 1
110 #define PERIPH_CLK_DDR 2 113 #define PERIPH_CLK_DDR 2
111 #define PERIPH_CLK_ROM 3 114 #define PERIPH_CLK_ROM 3
112 #define PERIPH_CLK_COUNTER_FAST 4 115 #define PERIPH_CLK_COUNTER_FAST 4
113 #define PERIPH_CLK_COUNTER_SLOW 5 116 #define PERIPH_CLK_COUNTER_SLOW 5
114 #define PERIPH_CLK_IR 6 117 #define PERIPH_CLK_IR 6
115 #define PERIPH_CLK_WD 7 118 #define PERIPH_CLK_WD 7
116 #define PERIPH_CLK_PDM 8 119 #define PERIPH_CLK_PDM 8
117 #define PERIPH_CLK_PWM 9 120 #define PERIPH_CLK_PWM 9
118 #define PERIPH_CLK_I2C0 10 121 #define PERIPH_CLK_I2C0 10
119 #define PERIPH_CLK_I2C1 11 122 #define PERIPH_CLK_I2C1 11
120 #define PERIPH_CLK_I2C2 12 123 #define PERIPH_CLK_I2C2 12
121 #define PERIPH_CLK_I2C3 13 124 #define PERIPH_CLK_I2C3 13
122 125
123 /* Peripheral divider clocks */ 126 /* Peripheral divider clocks */
124 #define PERIPH_CLK_ROM_DIV 32 127 #define PERIPH_CLK_ROM_DIV 32
125 #define PERIPH_CLK_COUNTER_FAST_DIV 33 128 #define PERIPH_CLK_COUNTER_FAST_DIV 33
126 #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34 129 #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34
127 #define PERIPH_CLK_COUNTER_SLOW_DIV 35 130 #define PERIPH_CLK_COUNTER_SLOW_DIV 35
128 #define PERIPH_CLK_IR_PRE_DIV 36 131 #define PERIPH_CLK_IR_PRE_DIV 36
129 #define PERIPH_CLK_IR_DIV 37 132 #define PERIPH_CLK_IR_DIV 37
130 #define PERIPH_CLK_WD_PRE_DIV 38 133 #define PERIPH_CLK_WD_PRE_DIV 38
131 #define PERIPH_CLK_WD_DIV 39 134 #define PERIPH_CLK_WD_DIV 39
132 #define PERIPH_CLK_PDM_PRE_DIV 40 135 #define PERIPH_CLK_PDM_PRE_DIV 40
133 #define PERIPH_CLK_PDM_DIV 41 136 #define PERIPH_CLK_PDM_DIV 41
134 #define PERIPH_CLK_PWM_PRE_DIV 42 137 #define PERIPH_CLK_PWM_PRE_DIV 42
135 #define PERIPH_CLK_PWM_DIV 43 138 #define PERIPH_CLK_PWM_DIV 43
136 #define PERIPH_CLK_I2C0_PRE_DIV 44 139 #define PERIPH_CLK_I2C0_PRE_DIV 44
137 #define PERIPH_CLK_I2C0_DIV 45 140 #define PERIPH_CLK_I2C0_DIV 45
138 #define PERIPH_CLK_I2C1_PRE_DIV 46 141 #define PERIPH_CLK_I2C1_PRE_DIV 46
139 #define PERIPH_CLK_I2C1_DIV 47 142 #define PERIPH_CLK_I2C1_DIV 47
140 #define PERIPH_CLK_I2C2_PRE_DIV 48 143 #define PERIPH_CLK_I2C2_PRE_DIV 48
141 #define PERIPH_CLK_I2C2_DIV 49 144 #define PERIPH_CLK_I2C2_DIV 49
142 #define PERIPH_CLK_I2C3_PRE_DIV 50 145 #define PERIPH_CLK_I2C3_PRE_DIV 50
143 #define PERIPH_CLK_I2C3_DIV 51 146 #define PERIPH_CLK_I2C3_DIV 51
144 147
145 #define PERIPH_CLK_NR_CLKS 52 148 #define PERIPH_CLK_NR_CLKS 52
146 149
147 /* System gate clocks */ 150 /* System gate clocks */
148 #define SYS_CLK_I2C0 0 151 #define SYS_CLK_I2C0 0
149 #define SYS_CLK_I2C1 1 152 #define SYS_CLK_I2C1 1
150 #define SYS_CLK_I2C2 2 153 #define SYS_CLK_I2C2 2
151 #define SYS_CLK_I2C3 3 154 #define SYS_CLK_I2C3 3
152 #define SYS_CLK_I2S_IN 4 155 #define SYS_CLK_I2S_IN 4
153 #define SYS_CLK_PAUD_OUT 5 156 #define SYS_CLK_PAUD_OUT 5
154 #define SYS_CLK_SPDIF_OUT 6 157 #define SYS_CLK_SPDIF_OUT 6
155 #define SYS_CLK_SPI0_MASTER 7 158 #define SYS_CLK_SPI0_MASTER 7
156 #define SYS_CLK_SPI0_SLAVE 8 159 #define SYS_CLK_SPI0_SLAVE 8
157 #define SYS_CLK_PWM 9 160 #define SYS_CLK_PWM 9
158 #define SYS_CLK_UART0 10 161 #define SYS_CLK_UART0 10
159 #define SYS_CLK_UART1 11 162 #define SYS_CLK_UART1 11
160 #define SYS_CLK_SPI1 12 163 #define SYS_CLK_SPI1 12
161 #define SYS_CLK_MDC 13 164 #define SYS_CLK_MDC 13
162 #define SYS_CLK_SD_HOST 14 165 #define SYS_CLK_SD_HOST 14
163 #define SYS_CLK_ENET 15 166 #define SYS_CLK_ENET 15
164 #define SYS_CLK_IR 16 167 #define SYS_CLK_IR 16
165 #define SYS_CLK_WD 17 168 #define SYS_CLK_WD 17
166 #define SYS_CLK_TIMER 18 169 #define SYS_CLK_TIMER 18
167 #define SYS_CLK_I2S_OUT 24 170 #define SYS_CLK_I2S_OUT 24
168 #define SYS_CLK_SPDIF_IN 25 171 #define SYS_CLK_SPDIF_IN 25
169 #define SYS_CLK_EVENT_TIMER 26 172 #define SYS_CLK_EVENT_TIMER 26
170 #define SYS_CLK_HASH 27 173 #define SYS_CLK_HASH 27
171 174
172 #define SYS_CLK_NR_CLKS 28 175 #define SYS_CLK_NR_CLKS 28
173 176
174 /* Gates for external input clocks */ 177 /* Gates for external input clocks */
175 #define EXT_CLK_AUDIO_IN 0 178 #define EXT_CLK_AUDIO_IN 0
176 #define EXT_CLK_ENET_IN 1 179 #define EXT_CLK_ENET_IN 1
177 180
178 #define EXT_CLK_NR_CLKS 2 181 #define EXT_CLK_NR_CLKS 2
179 182
180 #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */ 183 #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
181 184
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