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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/qcom,dispcc-sc7180.h

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Diff markup

Differences between /include/dt-bindings/clock/qcom,dispcc-sc7180.h (Architecture m68k) and /include/dt-bindings/clock/qcom,dispcc-sc7180.h (Architecture ppc)


  1 /* SPDX-License-Identifier: GPL-2.0-only */         1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*                                                  2 /*
  3  * Copyright (c) 2019, The Linux Foundation. A      3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  4  */                                                 4  */
  5                                                     5 
  6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H      6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
  7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H      7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
  8                                                     8 
  9 #define DISP_CC_PLL0                                9 #define DISP_CC_PLL0                            0
 10 #define DISP_CC_PLL0_OUT_EVEN                      10 #define DISP_CC_PLL0_OUT_EVEN                   1
 11 #define DISP_CC_MDSS_AHB_CLK                       11 #define DISP_CC_MDSS_AHB_CLK                    2
 12 #define DISP_CC_MDSS_AHB_CLK_SRC                   12 #define DISP_CC_MDSS_AHB_CLK_SRC                3
 13 #define DISP_CC_MDSS_BYTE0_CLK                     13 #define DISP_CC_MDSS_BYTE0_CLK                  4
 14 #define DISP_CC_MDSS_BYTE0_CLK_SRC                 14 #define DISP_CC_MDSS_BYTE0_CLK_SRC              5
 15 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC             15 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC          6
 16 #define DISP_CC_MDSS_BYTE0_INTF_CLK                16 #define DISP_CC_MDSS_BYTE0_INTF_CLK             7
 17 #define DISP_CC_MDSS_DP_AUX_CLK                    17 #define DISP_CC_MDSS_DP_AUX_CLK                 8
 18 #define DISP_CC_MDSS_DP_AUX_CLK_SRC                18 #define DISP_CC_MDSS_DP_AUX_CLK_SRC             9
 19 #define DISP_CC_MDSS_DP_CRYPTO_CLK                 19 #define DISP_CC_MDSS_DP_CRYPTO_CLK              10
 20 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC             20 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC          11
 21 #define DISP_CC_MDSS_DP_LINK_CLK                   21 #define DISP_CC_MDSS_DP_LINK_CLK                12
 22 #define DISP_CC_MDSS_DP_LINK_CLK_SRC               22 #define DISP_CC_MDSS_DP_LINK_CLK_SRC            13
 23 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC           23 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC        14
 24 #define DISP_CC_MDSS_DP_LINK_INTF_CLK              24 #define DISP_CC_MDSS_DP_LINK_INTF_CLK           15
 25 #define DISP_CC_MDSS_DP_PIXEL_CLK                  25 #define DISP_CC_MDSS_DP_PIXEL_CLK               16
 26 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC              26 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC           17
 27 #define DISP_CC_MDSS_ESC0_CLK                      27 #define DISP_CC_MDSS_ESC0_CLK                   18
 28 #define DISP_CC_MDSS_ESC0_CLK_SRC                  28 #define DISP_CC_MDSS_ESC0_CLK_SRC               19
 29 #define DISP_CC_MDSS_MDP_CLK                       29 #define DISP_CC_MDSS_MDP_CLK                    20
 30 #define DISP_CC_MDSS_MDP_CLK_SRC                   30 #define DISP_CC_MDSS_MDP_CLK_SRC                21
 31 #define DISP_CC_MDSS_MDP_LUT_CLK                   31 #define DISP_CC_MDSS_MDP_LUT_CLK                22
 32 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK              32 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK           23
 33 #define DISP_CC_MDSS_PCLK0_CLK                     33 #define DISP_CC_MDSS_PCLK0_CLK                  24
 34 #define DISP_CC_MDSS_PCLK0_CLK_SRC                 34 #define DISP_CC_MDSS_PCLK0_CLK_SRC              25
 35 #define DISP_CC_MDSS_ROT_CLK                       35 #define DISP_CC_MDSS_ROT_CLK                    26
 36 #define DISP_CC_MDSS_ROT_CLK_SRC                   36 #define DISP_CC_MDSS_ROT_CLK_SRC                27
 37 #define DISP_CC_MDSS_RSCC_AHB_CLK                  37 #define DISP_CC_MDSS_RSCC_AHB_CLK               28
 38 #define DISP_CC_MDSS_RSCC_VSYNC_CLK                38 #define DISP_CC_MDSS_RSCC_VSYNC_CLK             29
 39 #define DISP_CC_MDSS_VSYNC_CLK                     39 #define DISP_CC_MDSS_VSYNC_CLK                  30
 40 #define DISP_CC_MDSS_VSYNC_CLK_SRC                 40 #define DISP_CC_MDSS_VSYNC_CLK_SRC              31
 41 #define DISP_CC_XO_CLK                             41 #define DISP_CC_XO_CLK                          32
 42                                                    42 
 43 /* DISP_CC GDSCR */                                43 /* DISP_CC GDSCR */
 44 #define MDSS_GDSC                                  44 #define MDSS_GDSC                               0
 45                                                    45 
 46 #endif                                             46 #endif
 47                                                    47 

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