1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundati 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 6 #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 7 #define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 7 #define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H 8 8 9 /* DISP_CC clock registers */ 9 /* DISP_CC clock registers */ 10 #define DISP_CC_MDSS_AHB_CLK 10 #define DISP_CC_MDSS_AHB_CLK 0 11 #define DISP_CC_MDSS_AXI_CLK 11 #define DISP_CC_MDSS_AXI_CLK 1 12 #define DISP_CC_MDSS_BYTE0_CLK 12 #define DISP_CC_MDSS_BYTE0_CLK 2 13 #define DISP_CC_MDSS_BYTE0_CLK_SRC 13 #define DISP_CC_MDSS_BYTE0_CLK_SRC 3 14 #define DISP_CC_MDSS_BYTE0_INTF_CLK 14 #define DISP_CC_MDSS_BYTE0_INTF_CLK 4 15 #define DISP_CC_MDSS_BYTE1_CLK 15 #define DISP_CC_MDSS_BYTE1_CLK 5 16 #define DISP_CC_MDSS_BYTE1_CLK_SRC 16 #define DISP_CC_MDSS_BYTE1_CLK_SRC 6 17 #define DISP_CC_MDSS_BYTE1_INTF_CLK 17 #define DISP_CC_MDSS_BYTE1_INTF_CLK 7 18 #define DISP_CC_MDSS_ESC0_CLK 18 #define DISP_CC_MDSS_ESC0_CLK 8 19 #define DISP_CC_MDSS_ESC0_CLK_SRC 19 #define DISP_CC_MDSS_ESC0_CLK_SRC 9 20 #define DISP_CC_MDSS_ESC1_CLK 20 #define DISP_CC_MDSS_ESC1_CLK 10 21 #define DISP_CC_MDSS_ESC1_CLK_SRC 21 #define DISP_CC_MDSS_ESC1_CLK_SRC 11 22 #define DISP_CC_MDSS_MDP_CLK 22 #define DISP_CC_MDSS_MDP_CLK 12 23 #define DISP_CC_MDSS_MDP_CLK_SRC 23 #define DISP_CC_MDSS_MDP_CLK_SRC 13 24 #define DISP_CC_MDSS_MDP_LUT_CLK 24 #define DISP_CC_MDSS_MDP_LUT_CLK 14 25 #define DISP_CC_MDSS_PCLK0_CLK 25 #define DISP_CC_MDSS_PCLK0_CLK 15 26 #define DISP_CC_MDSS_PCLK0_CLK_SRC 26 #define DISP_CC_MDSS_PCLK0_CLK_SRC 16 27 #define DISP_CC_MDSS_PCLK1_CLK 27 #define DISP_CC_MDSS_PCLK1_CLK 17 28 #define DISP_CC_MDSS_PCLK1_CLK_SRC 28 #define DISP_CC_MDSS_PCLK1_CLK_SRC 18 29 #define DISP_CC_MDSS_ROT_CLK 29 #define DISP_CC_MDSS_ROT_CLK 19 30 #define DISP_CC_MDSS_ROT_CLK_SRC 30 #define DISP_CC_MDSS_ROT_CLK_SRC 20 31 #define DISP_CC_MDSS_RSCC_AHB_CLK 31 #define DISP_CC_MDSS_RSCC_AHB_CLK 21 32 #define DISP_CC_MDSS_RSCC_VSYNC_CLK 32 #define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 33 #define DISP_CC_MDSS_VSYNC_CLK 33 #define DISP_CC_MDSS_VSYNC_CLK 23 34 #define DISP_CC_MDSS_VSYNC_CLK_SRC 34 #define DISP_CC_MDSS_VSYNC_CLK_SRC 24 35 #define DISP_CC_PLL0 35 #define DISP_CC_PLL0 25 36 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 36 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 37 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 37 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 38 #define DISP_CC_MDSS_DP_AUX_CLK 38 #define DISP_CC_MDSS_DP_AUX_CLK 28 39 #define DISP_CC_MDSS_DP_AUX_CLK_SRC 39 #define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 40 #define DISP_CC_MDSS_DP_CRYPTO_CLK 40 #define DISP_CC_MDSS_DP_CRYPTO_CLK 30 41 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 41 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 42 #define DISP_CC_MDSS_DP_LINK_CLK 42 #define DISP_CC_MDSS_DP_LINK_CLK 32 43 #define DISP_CC_MDSS_DP_LINK_CLK_SRC 43 #define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 44 #define DISP_CC_MDSS_DP_LINK_INTF_CLK 44 #define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 45 #define DISP_CC_MDSS_DP_PIXEL1_CLK 45 #define DISP_CC_MDSS_DP_PIXEL1_CLK 35 46 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 46 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 47 #define DISP_CC_MDSS_DP_PIXEL_CLK 47 #define DISP_CC_MDSS_DP_PIXEL_CLK 37 48 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 48 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 49 49 50 /* DISP_CC Reset */ 50 /* DISP_CC Reset */ 51 #define DISP_CC_MDSS_RSCC_BCR 51 #define DISP_CC_MDSS_RSCC_BCR 0 52 52 53 /* DISP_CC GDSCR */ 53 /* DISP_CC GDSCR */ 54 #define MDSS_GDSC 54 #define MDSS_GDSC 0 55 55 56 #endif 56 #endif 57 57
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