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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/qcom,dispcc-sdm845.h

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Diff markup

Differences between /include/dt-bindings/clock/qcom,dispcc-sdm845.h (Version linux-6.12-rc7) and /include/dt-bindings/clock/qcom,dispcc-sdm845.h (Version linux-4.11.12)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 
  2 /*                                                
  3  * Copyright (c) 2018-2019, The Linux Foundati    
  4  */                                               
  5                                                   
  6 #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H     
  7 #define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H     
  8                                                   
  9 /* DISP_CC clock registers */                     
 10 #define DISP_CC_MDSS_AHB_CLK                      
 11 #define DISP_CC_MDSS_AXI_CLK                      
 12 #define DISP_CC_MDSS_BYTE0_CLK                    
 13 #define DISP_CC_MDSS_BYTE0_CLK_SRC                
 14 #define DISP_CC_MDSS_BYTE0_INTF_CLK               
 15 #define DISP_CC_MDSS_BYTE1_CLK                    
 16 #define DISP_CC_MDSS_BYTE1_CLK_SRC                
 17 #define DISP_CC_MDSS_BYTE1_INTF_CLK               
 18 #define DISP_CC_MDSS_ESC0_CLK                     
 19 #define DISP_CC_MDSS_ESC0_CLK_SRC                 
 20 #define DISP_CC_MDSS_ESC1_CLK                     
 21 #define DISP_CC_MDSS_ESC1_CLK_SRC                 
 22 #define DISP_CC_MDSS_MDP_CLK                      
 23 #define DISP_CC_MDSS_MDP_CLK_SRC                  
 24 #define DISP_CC_MDSS_MDP_LUT_CLK                  
 25 #define DISP_CC_MDSS_PCLK0_CLK                    
 26 #define DISP_CC_MDSS_PCLK0_CLK_SRC                
 27 #define DISP_CC_MDSS_PCLK1_CLK                    
 28 #define DISP_CC_MDSS_PCLK1_CLK_SRC                
 29 #define DISP_CC_MDSS_ROT_CLK                      
 30 #define DISP_CC_MDSS_ROT_CLK_SRC                  
 31 #define DISP_CC_MDSS_RSCC_AHB_CLK                 
 32 #define DISP_CC_MDSS_RSCC_VSYNC_CLK               
 33 #define DISP_CC_MDSS_VSYNC_CLK                    
 34 #define DISP_CC_MDSS_VSYNC_CLK_SRC                
 35 #define DISP_CC_PLL0                              
 36 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC            
 37 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC            
 38 #define DISP_CC_MDSS_DP_AUX_CLK                   
 39 #define DISP_CC_MDSS_DP_AUX_CLK_SRC               
 40 #define DISP_CC_MDSS_DP_CRYPTO_CLK                
 41 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC            
 42 #define DISP_CC_MDSS_DP_LINK_CLK                  
 43 #define DISP_CC_MDSS_DP_LINK_CLK_SRC              
 44 #define DISP_CC_MDSS_DP_LINK_INTF_CLK             
 45 #define DISP_CC_MDSS_DP_PIXEL1_CLK                
 46 #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC            
 47 #define DISP_CC_MDSS_DP_PIXEL_CLK                 
 48 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC             
 49                                                   
 50 /* DISP_CC Reset */                               
 51 #define DISP_CC_MDSS_RSCC_BCR                     
 52                                                   
 53 /* DISP_CC GDSCR */                               
 54 #define MDSS_GDSC                                 
 55                                                   
 56 #endif                                            
 57                                                   

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