1 /* Copyright (c) 2015 The Linux Foundation. Al 1 2 * 3 * Permission to use, copy, modify, and/or dis 4 * purpose with or without fee is hereby grant 5 * copyright notice and this permission notice 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AU 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SH 10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUEN 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA 12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TOR 13 * OR IN CONNECTION WITH THE USE OR PERFORMANC 14 * 15 */ 16 #ifndef __QCOM_CLK_IPQ4019_H__ 17 #define __QCOM_CLK_IPQ4019_H__ 18 19 #define GCC_DUMMY_CLK 20 #define AUDIO_CLK_SRC 21 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 22 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 23 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 24 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 25 #define BLSP1_UART1_APPS_CLK_SRC 26 #define BLSP1_UART2_APPS_CLK_SRC 27 #define GCC_USB3_MOCK_UTMI_CLK_SRC 28 #define GCC_APPS_CLK_SRC 29 #define GCC_APPS_AHB_CLK_SRC 30 #define GP1_CLK_SRC 31 #define GP2_CLK_SRC 32 #define GP3_CLK_SRC 33 #define SDCC1_APPS_CLK_SRC 34 #define FEPHY_125M_DLY_CLK_SRC 35 #define WCSS2G_CLK_SRC 36 #define WCSS5G_CLK_SRC 37 #define GCC_APSS_AHB_CLK 38 #define GCC_AUDIO_AHB_CLK 39 #define GCC_AUDIO_PWM_CLK 40 #define GCC_BLSP1_AHB_CLK 41 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 42 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 43 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 44 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 45 #define GCC_BLSP1_UART1_APPS_CLK 46 #define GCC_BLSP1_UART2_APPS_CLK 47 #define GCC_DCD_XO_CLK 48 #define GCC_GP1_CLK 49 #define GCC_GP2_CLK 50 #define GCC_GP3_CLK 51 #define GCC_BOOT_ROM_AHB_CLK 52 #define GCC_CRYPTO_AHB_CLK 53 #define GCC_CRYPTO_AXI_CLK 54 #define GCC_CRYPTO_CLK 55 #define GCC_ESS_CLK 56 #define GCC_IMEM_AXI_CLK 57 #define GCC_IMEM_CFG_AHB_CLK 58 #define GCC_PCIE_AHB_CLK 59 #define GCC_PCIE_AXI_M_CLK 60 #define GCC_PCIE_AXI_S_CLK 61 #define GCC_PCNOC_AHB_CLK 62 #define GCC_PRNG_AHB_CLK 63 #define GCC_QPIC_AHB_CLK 64 #define GCC_QPIC_CLK 65 #define GCC_SDCC1_AHB_CLK 66 #define GCC_SDCC1_APPS_CLK 67 #define GCC_SNOC_PCNOC_AHB_CLK 68 #define GCC_SYS_NOC_125M_CLK 69 #define GCC_SYS_NOC_AXI_CLK 70 #define GCC_TCSR_AHB_CLK 71 #define GCC_TLMM_AHB_CLK 72 #define GCC_USB2_MASTER_CLK 73 #define GCC_USB2_SLEEP_CLK 74 #define GCC_USB2_MOCK_UTMI_CLK 75 #define GCC_USB3_MASTER_CLK 76 #define GCC_USB3_SLEEP_CLK 77 #define GCC_USB3_MOCK_UTMI_CLK 78 #define GCC_WCSS2G_CLK 79 #define GCC_WCSS2G_REF_CLK 80 #define GCC_WCSS2G_RTC_CLK 81 #define GCC_WCSS5G_CLK 82 #define GCC_WCSS5G_REF_CLK 83 #define GCC_WCSS5G_RTC_CLK 84 #define GCC_APSS_DDRPLL_VCO 85 #define GCC_SDCC_PLLDIV_CLK 86 #define GCC_FEPLL_VCO 87 #define GCC_FEPLL125_CLK 88 #define GCC_FEPLL125DLY_CLK 89 #define GCC_FEPLL200_CLK 90 #define GCC_FEPLL500_CLK 91 #define GCC_FEPLL_WCSS2G_CLK 92 #define GCC_FEPLL_WCSS5G_CLK 93 #define GCC_APSS_CPU_PLLDIV_CLK 94 #define GCC_PCNOC_AHB_CLK_SRC 95 96 #define WIFI0_CPU_INIT_RESET 97 #define WIFI0_RADIO_SRIF_RESET 98 #define WIFI0_RADIO_WARM_RESET 99 #define WIFI0_RADIO_COLD_RESET 100 #define WIFI0_CORE_WARM_RESET 101 #define WIFI0_CORE_COLD_RESET 102 #define WIFI1_CPU_INIT_RESET 103 #define WIFI1_RADIO_SRIF_RESET 104 #define WIFI1_RADIO_WARM_RESET 105 #define WIFI1_RADIO_COLD_RESET 106 #define WIFI1_CORE_WARM_RESET 107 #define WIFI1_CORE_COLD_RESET 108 #define USB3_UNIPHY_PHY_ARES 109 #define USB3_HSPHY_POR_ARES 110 #define USB3_HSPHY_S_ARES 111 #define USB2_HSPHY_POR_ARES 112 #define USB2_HSPHY_S_ARES 113 #define PCIE_PHY_AHB_ARES 114 #define PCIE_AHB_ARES 115 #define PCIE_PWR_ARES 116 #define PCIE_PIPE_STICKY_ARES 117 #define PCIE_AXI_M_STICKY_ARES 118 #define PCIE_PHY_ARES 119 #define PCIE_PARF_XPU_ARES 120 #define PCIE_AXI_S_XPU_ARES 121 #define PCIE_AXI_M_VMIDMT_ARES 122 #define PCIE_PIPE_ARES 123 #define PCIE_AXI_S_ARES 124 #define PCIE_AXI_M_ARES 125 #define ESS_RESET 126 #define GCC_BLSP1_BCR 127 #define GCC_BLSP1_QUP1_BCR 128 #define GCC_BLSP1_UART1_BCR 129 #define GCC_BLSP1_QUP2_BCR 130 #define GCC_BLSP1_UART2_BCR 131 #define GCC_BIMC_BCR 132 #define GCC_TLMM_BCR 133 #define GCC_IMEM_BCR 134 #define GCC_ESS_BCR 135 #define GCC_PRNG_BCR 136 #define GCC_BOOT_ROM_BCR 137 #define GCC_CRYPTO_BCR 138 #define GCC_SDCC1_BCR 139 #define GCC_SEC_CTRL_BCR 140 #define GCC_AUDIO_BCR 141 #define GCC_QPIC_BCR 142 #define GCC_PCIE_BCR 143 #define GCC_USB2_BCR 144 #define GCC_USB2_PHY_BCR 145 #define GCC_USB3_BCR 146 #define GCC_USB3_PHY_BCR 147 #define GCC_SYSTEM_NOC_BCR 148 #define GCC_PCNOC_BCR 149 #define GCC_DCD_BCR 150 #define GCC_SNOC_BUS_TIMEOUT0_BCR 151 #define GCC_SNOC_BUS_TIMEOUT1_BCR 152 #define GCC_SNOC_BUS_TIMEOUT2_BCR 153 #define GCC_SNOC_BUS_TIMEOUT3_BCR 154 #define GCC_PCNOC_BUS_TIMEOUT0_BCR 155 #define GCC_PCNOC_BUS_TIMEOUT1_BCR 156 #define GCC_PCNOC_BUS_TIMEOUT2_BCR 157 #define GCC_PCNOC_BUS_TIMEOUT3_BCR 158 #define GCC_PCNOC_BUS_TIMEOUT4_BCR 159 #define GCC_PCNOC_BUS_TIMEOUT5_BCR 160 #define GCC_PCNOC_BUS_TIMEOUT6_BCR 161 #define GCC_PCNOC_BUS_TIMEOUT7_BCR 162 #define GCC_PCNOC_BUS_TIMEOUT8_BCR 163 #define GCC_PCNOC_BUS_TIMEOUT9_BCR 164 #define GCC_TCSR_BCR 165 #define GCC_QDSS_BCR 166 #define GCC_MPM_BCR 167 #define GCC_SPDM_BCR 168 #define ESS_MAC1_ARES 169 #define ESS_MAC2_ARES 170 #define ESS_MAC3_ARES 171 #define ESS_MAC4_ARES 172 #define ESS_MAC5_ARES 173 #define ESS_PSGMII_ARES 174 175 #endif 176
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