1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (c) 2013, The Linux Foundation. A 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * Copyright (c) BayLibre, SAS. 3 * Copyright (c) BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibr 4 * Author : Neil Armstrong <narmstrong@baylibre.com>
>> 5 *
>> 6 * This software is licensed under the terms of the GNU General Public
>> 7 * License version 2, as published by the Free Software Foundation, and
>> 8 * may be copied, distributed, and modified under those terms.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
6 */ 14 */
7 15
8 #ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H 16 #ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H
9 #define _DT_BINDINGS_CLK_MDM_GCC_9615_H 17 #define _DT_BINDINGS_CLK_MDM_GCC_9615_H
10 18
11 #define AFAB_CLK_SRC 19 #define AFAB_CLK_SRC 0
12 #define AFAB_CORE_CLK 20 #define AFAB_CORE_CLK 1
13 #define SFAB_MSS_Q6_SW_A_CLK 21 #define SFAB_MSS_Q6_SW_A_CLK 2
14 #define SFAB_MSS_Q6_FW_A_CLK 22 #define SFAB_MSS_Q6_FW_A_CLK 3
15 #define QDSS_STM_CLK 23 #define QDSS_STM_CLK 4
16 #define SCSS_A_CLK 24 #define SCSS_A_CLK 5
17 #define SCSS_H_CLK 25 #define SCSS_H_CLK 6
18 #define SCSS_XO_SRC_CLK 26 #define SCSS_XO_SRC_CLK 7
19 #define AFAB_EBI1_CH0_A_CLK 27 #define AFAB_EBI1_CH0_A_CLK 8
20 #define AFAB_EBI1_CH1_A_CLK 28 #define AFAB_EBI1_CH1_A_CLK 9
21 #define AFAB_AXI_S0_FCLK 29 #define AFAB_AXI_S0_FCLK 10
22 #define AFAB_AXI_S1_FCLK 30 #define AFAB_AXI_S1_FCLK 11
23 #define AFAB_AXI_S2_FCLK 31 #define AFAB_AXI_S2_FCLK 12
24 #define AFAB_AXI_S3_FCLK 32 #define AFAB_AXI_S3_FCLK 13
25 #define AFAB_AXI_S4_FCLK 33 #define AFAB_AXI_S4_FCLK 14
26 #define SFAB_CORE_CLK 34 #define SFAB_CORE_CLK 15
27 #define SFAB_AXI_S0_FCLK 35 #define SFAB_AXI_S0_FCLK 16
28 #define SFAB_AXI_S1_FCLK 36 #define SFAB_AXI_S1_FCLK 17
29 #define SFAB_AXI_S2_FCLK 37 #define SFAB_AXI_S2_FCLK 18
30 #define SFAB_AXI_S3_FCLK 38 #define SFAB_AXI_S3_FCLK 19
31 #define SFAB_AXI_S4_FCLK 39 #define SFAB_AXI_S4_FCLK 20
32 #define SFAB_AHB_S0_FCLK 40 #define SFAB_AHB_S0_FCLK 21
33 #define SFAB_AHB_S1_FCLK 41 #define SFAB_AHB_S1_FCLK 22
34 #define SFAB_AHB_S2_FCLK 42 #define SFAB_AHB_S2_FCLK 23
35 #define SFAB_AHB_S3_FCLK 43 #define SFAB_AHB_S3_FCLK 24
36 #define SFAB_AHB_S4_FCLK 44 #define SFAB_AHB_S4_FCLK 25
37 #define SFAB_AHB_S5_FCLK 45 #define SFAB_AHB_S5_FCLK 26
38 #define SFAB_AHB_S6_FCLK 46 #define SFAB_AHB_S6_FCLK 27
39 #define SFAB_AHB_S7_FCLK 47 #define SFAB_AHB_S7_FCLK 28
40 #define QDSS_AT_CLK_SRC 48 #define QDSS_AT_CLK_SRC 29
41 #define QDSS_AT_CLK 49 #define QDSS_AT_CLK 30
42 #define QDSS_TRACECLKIN_CLK_SRC 50 #define QDSS_TRACECLKIN_CLK_SRC 31
43 #define QDSS_TRACECLKIN_CLK 51 #define QDSS_TRACECLKIN_CLK 32
44 #define QDSS_TSCTR_CLK_SRC 52 #define QDSS_TSCTR_CLK_SRC 33
45 #define QDSS_TSCTR_CLK 53 #define QDSS_TSCTR_CLK 34
46 #define SFAB_ADM0_M0_A_CLK 54 #define SFAB_ADM0_M0_A_CLK 35
47 #define SFAB_ADM0_M1_A_CLK 55 #define SFAB_ADM0_M1_A_CLK 36
48 #define SFAB_ADM0_M2_H_CLK 56 #define SFAB_ADM0_M2_H_CLK 37
49 #define ADM0_CLK 57 #define ADM0_CLK 38
50 #define ADM0_PBUS_CLK 58 #define ADM0_PBUS_CLK 39
51 #define MSS_XPU_CLK 59 #define MSS_XPU_CLK 40
52 #define IMEM0_A_CLK 60 #define IMEM0_A_CLK 41
53 #define QDSS_H_CLK 61 #define QDSS_H_CLK 42
54 #define PCIE_A_CLK 62 #define PCIE_A_CLK 43
55 #define PCIE_AUX_CLK 63 #define PCIE_AUX_CLK 44
56 #define PCIE_PHY_REF_CLK 64 #define PCIE_PHY_REF_CLK 45
57 #define PCIE_H_CLK 65 #define PCIE_H_CLK 46
58 #define SFAB_CLK_SRC 66 #define SFAB_CLK_SRC 47
59 #define MAHB0_CLK 67 #define MAHB0_CLK 48
60 #define Q6SW_CLK_SRC 68 #define Q6SW_CLK_SRC 49
61 #define Q6SW_CLK 69 #define Q6SW_CLK 50
62 #define Q6FW_CLK_SRC 70 #define Q6FW_CLK_SRC 51
63 #define Q6FW_CLK 71 #define Q6FW_CLK 52
64 #define SFAB_MSS_M_A_CLK 72 #define SFAB_MSS_M_A_CLK 53
65 #define SFAB_USB3_M_A_CLK 73 #define SFAB_USB3_M_A_CLK 54
66 #define SFAB_LPASS_Q6_A_CLK 74 #define SFAB_LPASS_Q6_A_CLK 55
67 #define SFAB_AFAB_M_A_CLK 75 #define SFAB_AFAB_M_A_CLK 56
68 #define AFAB_SFAB_M0_A_CLK 76 #define AFAB_SFAB_M0_A_CLK 57
69 #define AFAB_SFAB_M1_A_CLK 77 #define AFAB_SFAB_M1_A_CLK 58
70 #define SFAB_SATA_S_H_CLK 78 #define SFAB_SATA_S_H_CLK 59
71 #define DFAB_CLK_SRC 79 #define DFAB_CLK_SRC 60
72 #define DFAB_CLK 80 #define DFAB_CLK 61
73 #define SFAB_DFAB_M_A_CLK 81 #define SFAB_DFAB_M_A_CLK 62
74 #define DFAB_SFAB_M_A_CLK 82 #define DFAB_SFAB_M_A_CLK 63
75 #define DFAB_SWAY0_H_CLK 83 #define DFAB_SWAY0_H_CLK 64
76 #define DFAB_SWAY1_H_CLK 84 #define DFAB_SWAY1_H_CLK 65
77 #define DFAB_ARB0_H_CLK 85 #define DFAB_ARB0_H_CLK 66
78 #define DFAB_ARB1_H_CLK 86 #define DFAB_ARB1_H_CLK 67
79 #define PPSS_H_CLK 87 #define PPSS_H_CLK 68
80 #define PPSS_PROC_CLK 88 #define PPSS_PROC_CLK 69
81 #define PPSS_TIMER0_CLK 89 #define PPSS_TIMER0_CLK 70
82 #define PPSS_TIMER1_CLK 90 #define PPSS_TIMER1_CLK 71
83 #define PMEM_A_CLK 91 #define PMEM_A_CLK 72
84 #define DMA_BAM_H_CLK 92 #define DMA_BAM_H_CLK 73
85 #define SIC_H_CLK 93 #define SIC_H_CLK 74
86 #define SPS_TIC_H_CLK 94 #define SPS_TIC_H_CLK 75
87 #define SLIMBUS_H_CLK 95 #define SLIMBUS_H_CLK 76
88 #define SLIMBUS_XO_SRC_CLK 96 #define SLIMBUS_XO_SRC_CLK 77
89 #define CFPB_2X_CLK_SRC 97 #define CFPB_2X_CLK_SRC 78
90 #define CFPB_CLK 98 #define CFPB_CLK 79
91 #define CFPB0_H_CLK 99 #define CFPB0_H_CLK 80
92 #define CFPB1_H_CLK 100 #define CFPB1_H_CLK 81
93 #define CFPB2_H_CLK 101 #define CFPB2_H_CLK 82
94 #define SFAB_CFPB_M_H_CLK 102 #define SFAB_CFPB_M_H_CLK 83
95 #define CFPB_MASTER_H_CLK 103 #define CFPB_MASTER_H_CLK 84
96 #define SFAB_CFPB_S_H_CLK 104 #define SFAB_CFPB_S_H_CLK 85
97 #define CFPB_SPLITTER_H_CLK 105 #define CFPB_SPLITTER_H_CLK 86
98 #define TSIF_H_CLK 106 #define TSIF_H_CLK 87
99 #define TSIF_INACTIVITY_TIMERS_CLK 107 #define TSIF_INACTIVITY_TIMERS_CLK 88
100 #define TSIF_REF_SRC 108 #define TSIF_REF_SRC 89
101 #define TSIF_REF_CLK 109 #define TSIF_REF_CLK 90
102 #define CE1_H_CLK 110 #define CE1_H_CLK 91
103 #define CE1_CORE_CLK 111 #define CE1_CORE_CLK 92
104 #define CE1_SLEEP_CLK 112 #define CE1_SLEEP_CLK 93
105 #define CE2_H_CLK 113 #define CE2_H_CLK 94
106 #define CE2_CORE_CLK 114 #define CE2_CORE_CLK 95
107 #define SFPB_H_CLK_SRC 115 #define SFPB_H_CLK_SRC 97
108 #define SFPB_H_CLK 116 #define SFPB_H_CLK 98
109 #define SFAB_SFPB_M_H_CLK 117 #define SFAB_SFPB_M_H_CLK 99
110 #define SFAB_SFPB_S_H_CLK 118 #define SFAB_SFPB_S_H_CLK 100
111 #define RPM_PROC_CLK 119 #define RPM_PROC_CLK 101
112 #define RPM_BUS_H_CLK 120 #define RPM_BUS_H_CLK 102
113 #define RPM_SLEEP_CLK 121 #define RPM_SLEEP_CLK 103
114 #define RPM_TIMER_CLK 122 #define RPM_TIMER_CLK 104
115 #define RPM_MSG_RAM_H_CLK 123 #define RPM_MSG_RAM_H_CLK 105
116 #define PMIC_ARB0_H_CLK 124 #define PMIC_ARB0_H_CLK 106
117 #define PMIC_ARB1_H_CLK 125 #define PMIC_ARB1_H_CLK 107
118 #define PMIC_SSBI2_SRC 126 #define PMIC_SSBI2_SRC 108
119 #define PMIC_SSBI2_CLK 127 #define PMIC_SSBI2_CLK 109
120 #define SDC1_H_CLK 128 #define SDC1_H_CLK 110
121 #define SDC2_H_CLK 129 #define SDC2_H_CLK 111
122 #define SDC3_H_CLK 130 #define SDC3_H_CLK 112
123 #define SDC4_H_CLK 131 #define SDC4_H_CLK 113
124 #define SDC5_H_CLK 132 #define SDC5_H_CLK 114
125 #define SDC1_SRC 133 #define SDC1_SRC 115
126 #define SDC2_SRC 134 #define SDC2_SRC 116
127 #define SDC3_SRC 135 #define SDC3_SRC 117
128 #define SDC4_SRC 136 #define SDC4_SRC 118
129 #define SDC5_SRC 137 #define SDC5_SRC 119
130 #define SDC1_CLK 138 #define SDC1_CLK 120
131 #define SDC2_CLK 139 #define SDC2_CLK 121
132 #define SDC3_CLK 140 #define SDC3_CLK 122
133 #define SDC4_CLK 141 #define SDC4_CLK 123
134 #define SDC5_CLK 142 #define SDC5_CLK 124
135 #define DFAB_A2_H_CLK 143 #define DFAB_A2_H_CLK 125
136 #define USB_HS1_H_CLK 144 #define USB_HS1_H_CLK 126
137 #define USB_HS1_XCVR_SRC 145 #define USB_HS1_XCVR_SRC 127
138 #define USB_HS1_XCVR_CLK 146 #define USB_HS1_XCVR_CLK 128
139 #define USB_HSIC_H_CLK 147 #define USB_HSIC_H_CLK 129
140 #define USB_HSIC_XCVR_FS_SRC 148 #define USB_HSIC_XCVR_FS_SRC 130
141 #define USB_HSIC_XCVR_FS_CLK 149 #define USB_HSIC_XCVR_FS_CLK 131
142 #define USB_HSIC_SYSTEM_CLK_SRC 150 #define USB_HSIC_SYSTEM_CLK_SRC 132
143 #define USB_HSIC_SYSTEM_CLK 151 #define USB_HSIC_SYSTEM_CLK 133
144 #define CFPB0_C0_H_CLK 152 #define CFPB0_C0_H_CLK 134
145 #define CFPB0_C1_H_CLK 153 #define CFPB0_C1_H_CLK 135
146 #define CFPB0_D0_H_CLK 154 #define CFPB0_D0_H_CLK 136
147 #define CFPB0_D1_H_CLK 155 #define CFPB0_D1_H_CLK 137
148 #define USB_FS1_H_CLK 156 #define USB_FS1_H_CLK 138
149 #define USB_FS1_XCVR_FS_SRC 157 #define USB_FS1_XCVR_FS_SRC 139
150 #define USB_FS1_XCVR_FS_CLK 158 #define USB_FS1_XCVR_FS_CLK 140
151 #define USB_FS1_SYSTEM_CLK 159 #define USB_FS1_SYSTEM_CLK 141
152 #define USB_FS2_H_CLK 160 #define USB_FS2_H_CLK 142
153 #define USB_FS2_XCVR_FS_SRC 161 #define USB_FS2_XCVR_FS_SRC 143
154 #define USB_FS2_XCVR_FS_CLK 162 #define USB_FS2_XCVR_FS_CLK 144
155 #define USB_FS2_SYSTEM_CLK 163 #define USB_FS2_SYSTEM_CLK 145
156 #define GSBI_COMMON_SIM_SRC 164 #define GSBI_COMMON_SIM_SRC 146
157 #define GSBI1_H_CLK 165 #define GSBI1_H_CLK 147
158 #define GSBI2_H_CLK 166 #define GSBI2_H_CLK 148
159 #define GSBI3_H_CLK 167 #define GSBI3_H_CLK 149
160 #define GSBI4_H_CLK 168 #define GSBI4_H_CLK 150
161 #define GSBI5_H_CLK 169 #define GSBI5_H_CLK 151
162 #define GSBI6_H_CLK 170 #define GSBI6_H_CLK 152
163 #define GSBI7_H_CLK 171 #define GSBI7_H_CLK 153
164 #define GSBI8_H_CLK 172 #define GSBI8_H_CLK 154
165 #define GSBI9_H_CLK 173 #define GSBI9_H_CLK 155
166 #define GSBI10_H_CLK 174 #define GSBI10_H_CLK 156
167 #define GSBI11_H_CLK 175 #define GSBI11_H_CLK 157
168 #define GSBI12_H_CLK 176 #define GSBI12_H_CLK 158
169 #define GSBI1_UART_SRC 177 #define GSBI1_UART_SRC 159
170 #define GSBI1_UART_CLK 178 #define GSBI1_UART_CLK 160
171 #define GSBI2_UART_SRC 179 #define GSBI2_UART_SRC 161
172 #define GSBI2_UART_CLK 180 #define GSBI2_UART_CLK 162
173 #define GSBI3_UART_SRC 181 #define GSBI3_UART_SRC 163
174 #define GSBI3_UART_CLK 182 #define GSBI3_UART_CLK 164
175 #define GSBI4_UART_SRC 183 #define GSBI4_UART_SRC 165
176 #define GSBI4_UART_CLK 184 #define GSBI4_UART_CLK 166
177 #define GSBI5_UART_SRC 185 #define GSBI5_UART_SRC 167
178 #define GSBI5_UART_CLK 186 #define GSBI5_UART_CLK 168
179 #define GSBI6_UART_SRC 187 #define GSBI6_UART_SRC 169
180 #define GSBI6_UART_CLK 188 #define GSBI6_UART_CLK 170
181 #define GSBI7_UART_SRC 189 #define GSBI7_UART_SRC 171
182 #define GSBI7_UART_CLK 190 #define GSBI7_UART_CLK 172
183 #define GSBI8_UART_SRC 191 #define GSBI8_UART_SRC 173
184 #define GSBI8_UART_CLK 192 #define GSBI8_UART_CLK 174
185 #define GSBI9_UART_SRC 193 #define GSBI9_UART_SRC 175
186 #define GSBI9_UART_CLK 194 #define GSBI9_UART_CLK 176
187 #define GSBI10_UART_SRC 195 #define GSBI10_UART_SRC 177
188 #define GSBI10_UART_CLK 196 #define GSBI10_UART_CLK 178
189 #define GSBI11_UART_SRC 197 #define GSBI11_UART_SRC 179
190 #define GSBI11_UART_CLK 198 #define GSBI11_UART_CLK 180
191 #define GSBI12_UART_SRC 199 #define GSBI12_UART_SRC 181
192 #define GSBI12_UART_CLK 200 #define GSBI12_UART_CLK 182
193 #define GSBI1_QUP_SRC 201 #define GSBI1_QUP_SRC 183
194 #define GSBI1_QUP_CLK 202 #define GSBI1_QUP_CLK 184
195 #define GSBI2_QUP_SRC 203 #define GSBI2_QUP_SRC 185
196 #define GSBI2_QUP_CLK 204 #define GSBI2_QUP_CLK 186
197 #define GSBI3_QUP_SRC 205 #define GSBI3_QUP_SRC 187
198 #define GSBI3_QUP_CLK 206 #define GSBI3_QUP_CLK 188
199 #define GSBI4_QUP_SRC 207 #define GSBI4_QUP_SRC 189
200 #define GSBI4_QUP_CLK 208 #define GSBI4_QUP_CLK 190
201 #define GSBI5_QUP_SRC 209 #define GSBI5_QUP_SRC 191
202 #define GSBI5_QUP_CLK 210 #define GSBI5_QUP_CLK 192
203 #define GSBI6_QUP_SRC 211 #define GSBI6_QUP_SRC 193
204 #define GSBI6_QUP_CLK 212 #define GSBI6_QUP_CLK 194
205 #define GSBI7_QUP_SRC 213 #define GSBI7_QUP_SRC 195
206 #define GSBI7_QUP_CLK 214 #define GSBI7_QUP_CLK 196
207 #define GSBI8_QUP_SRC 215 #define GSBI8_QUP_SRC 197
208 #define GSBI8_QUP_CLK 216 #define GSBI8_QUP_CLK 198
209 #define GSBI9_QUP_SRC 217 #define GSBI9_QUP_SRC 199
210 #define GSBI9_QUP_CLK 218 #define GSBI9_QUP_CLK 200
211 #define GSBI10_QUP_SRC 219 #define GSBI10_QUP_SRC 201
212 #define GSBI10_QUP_CLK 220 #define GSBI10_QUP_CLK 202
213 #define GSBI11_QUP_SRC 221 #define GSBI11_QUP_SRC 203
214 #define GSBI11_QUP_CLK 222 #define GSBI11_QUP_CLK 204
215 #define GSBI12_QUP_SRC 223 #define GSBI12_QUP_SRC 205
216 #define GSBI12_QUP_CLK 224 #define GSBI12_QUP_CLK 206
217 #define GSBI1_SIM_CLK 225 #define GSBI1_SIM_CLK 207
218 #define GSBI2_SIM_CLK 226 #define GSBI2_SIM_CLK 208
219 #define GSBI3_SIM_CLK 227 #define GSBI3_SIM_CLK 209
220 #define GSBI4_SIM_CLK 228 #define GSBI4_SIM_CLK 210
221 #define GSBI5_SIM_CLK 229 #define GSBI5_SIM_CLK 211
222 #define GSBI6_SIM_CLK 230 #define GSBI6_SIM_CLK 212
223 #define GSBI7_SIM_CLK 231 #define GSBI7_SIM_CLK 213
224 #define GSBI8_SIM_CLK 232 #define GSBI8_SIM_CLK 214
225 #define GSBI9_SIM_CLK 233 #define GSBI9_SIM_CLK 215
226 #define GSBI10_SIM_CLK 234 #define GSBI10_SIM_CLK 216
227 #define GSBI11_SIM_CLK 235 #define GSBI11_SIM_CLK 217
228 #define GSBI12_SIM_CLK 236 #define GSBI12_SIM_CLK 218
229 #define USB_HSIC_HSIC_CLK_SRC 237 #define USB_HSIC_HSIC_CLK_SRC 219
230 #define USB_HSIC_HSIC_CLK 238 #define USB_HSIC_HSIC_CLK 220
231 #define USB_HSIC_HSIO_CAL_CLK 239 #define USB_HSIC_HSIO_CAL_CLK 221
232 #define SPDM_CFG_H_CLK 240 #define SPDM_CFG_H_CLK 222
233 #define SPDM_MSTR_H_CLK 241 #define SPDM_MSTR_H_CLK 223
234 #define SPDM_FF_CLK_SRC 242 #define SPDM_FF_CLK_SRC 224
235 #define SPDM_FF_CLK 243 #define SPDM_FF_CLK 225
236 #define SEC_CTRL_CLK 244 #define SEC_CTRL_CLK 226
237 #define SEC_CTRL_ACC_CLK_SRC 245 #define SEC_CTRL_ACC_CLK_SRC 227
238 #define SEC_CTRL_ACC_CLK 246 #define SEC_CTRL_ACC_CLK 228
239 #define TLMM_H_CLK 247 #define TLMM_H_CLK 229
240 #define TLMM_CLK 248 #define TLMM_CLK 230
241 #define SFAB_MSS_S_H_CLK 249 #define SFAB_MSS_S_H_CLK 231
242 #define MSS_SLP_CLK 250 #define MSS_SLP_CLK 232
243 #define MSS_Q6SW_JTAG_CLK 251 #define MSS_Q6SW_JTAG_CLK 233
244 #define MSS_Q6FW_JTAG_CLK 252 #define MSS_Q6FW_JTAG_CLK 234
245 #define MSS_S_H_CLK 253 #define MSS_S_H_CLK 235
246 #define MSS_CXO_SRC_CLK 254 #define MSS_CXO_SRC_CLK 236
247 #define SATA_H_CLK 255 #define SATA_H_CLK 237
248 #define SATA_CLK_SRC 256 #define SATA_CLK_SRC 238
249 #define SATA_RXOOB_CLK 257 #define SATA_RXOOB_CLK 239
250 #define SATA_PMALIVE_CLK 258 #define SATA_PMALIVE_CLK 240
251 #define SATA_PHY_REF_CLK 259 #define SATA_PHY_REF_CLK 241
252 #define TSSC_CLK_SRC 260 #define TSSC_CLK_SRC 242
253 #define TSSC_CLK 261 #define TSSC_CLK 243
254 #define PDM_SRC 262 #define PDM_SRC 244
255 #define PDM_CLK 263 #define PDM_CLK 245
256 #define GP0_SRC 264 #define GP0_SRC 246
257 #define GP0_CLK 265 #define GP0_CLK 247
258 #define GP1_SRC 266 #define GP1_SRC 248
259 #define GP1_CLK 267 #define GP1_CLK 249
260 #define GP2_SRC 268 #define GP2_SRC 250
261 #define GP2_CLK 269 #define GP2_CLK 251
262 #define MPM_CLK 270 #define MPM_CLK 252
263 #define EBI1_CLK_SRC 271 #define EBI1_CLK_SRC 253
264 #define EBI1_CH0_CLK 272 #define EBI1_CH0_CLK 254
265 #define EBI1_CH1_CLK 273 #define EBI1_CH1_CLK 255
266 #define EBI1_2X_CLK 274 #define EBI1_2X_CLK 256
267 #define EBI1_CH0_DQ_CLK 275 #define EBI1_CH0_DQ_CLK 257
268 #define EBI1_CH1_DQ_CLK 276 #define EBI1_CH1_DQ_CLK 258
269 #define EBI1_CH0_CA_CLK 277 #define EBI1_CH0_CA_CLK 259
270 #define EBI1_CH1_CA_CLK 278 #define EBI1_CH1_CA_CLK 260
271 #define EBI1_XO_CLK 279 #define EBI1_XO_CLK 261
272 #define SFAB_SMPSS_S_H_CLK 280 #define SFAB_SMPSS_S_H_CLK 262
273 #define PRNG_SRC 281 #define PRNG_SRC 263
274 #define PRNG_CLK 282 #define PRNG_CLK 264
275 #define PXO_SRC 283 #define PXO_SRC 265
276 #define LPASS_CXO_CLK 284 #define LPASS_CXO_CLK 266
277 #define LPASS_PXO_CLK 285 #define LPASS_PXO_CLK 267
278 #define SPDM_CY_PORT0_CLK 286 #define SPDM_CY_PORT0_CLK 268
279 #define SPDM_CY_PORT1_CLK 287 #define SPDM_CY_PORT1_CLK 269
280 #define SPDM_CY_PORT2_CLK 288 #define SPDM_CY_PORT2_CLK 270
281 #define SPDM_CY_PORT3_CLK 289 #define SPDM_CY_PORT3_CLK 271
282 #define SPDM_CY_PORT4_CLK 290 #define SPDM_CY_PORT4_CLK 272
283 #define SPDM_CY_PORT5_CLK 291 #define SPDM_CY_PORT5_CLK 273
284 #define SPDM_CY_PORT6_CLK 292 #define SPDM_CY_PORT6_CLK 274
285 #define SPDM_CY_PORT7_CLK 293 #define SPDM_CY_PORT7_CLK 275
286 #define PLL0 294 #define PLL0 276
287 #define PLL0_VOTE 295 #define PLL0_VOTE 277
288 #define PLL3 296 #define PLL3 278
289 #define PLL3_VOTE 297 #define PLL3_VOTE 279
290 #define PLL4_VOTE 298 #define PLL4_VOTE 280
291 #define PLL5 299 #define PLL5 281
292 #define PLL5_VOTE 300 #define PLL5_VOTE 282
293 #define PLL6 301 #define PLL6 283
294 #define PLL6_VOTE 302 #define PLL6_VOTE 284
295 #define PLL7_VOTE 303 #define PLL7_VOTE 285
296 #define PLL8 304 #define PLL8 286
297 #define PLL8_VOTE 305 #define PLL8_VOTE 287
298 #define PLL9 306 #define PLL9 288
299 #define PLL10 307 #define PLL10 289
300 #define PLL11 308 #define PLL11 290
301 #define PLL12 309 #define PLL12 291
302 #define PLL13 310 #define PLL13 292
303 #define PLL14 311 #define PLL14 293
304 #define PLL14_VOTE 312 #define PLL14_VOTE 294
305 #define USB_HS3_H_CLK 313 #define USB_HS3_H_CLK 295
306 #define USB_HS3_XCVR_SRC 314 #define USB_HS3_XCVR_SRC 296
307 #define USB_HS3_XCVR_CLK 315 #define USB_HS3_XCVR_CLK 297
308 #define USB_HS4_H_CLK 316 #define USB_HS4_H_CLK 298
309 #define USB_HS4_XCVR_SRC 317 #define USB_HS4_XCVR_SRC 299
310 #define USB_HS4_XCVR_CLK 318 #define USB_HS4_XCVR_CLK 300
311 #define SATA_PHY_CFG_CLK 319 #define SATA_PHY_CFG_CLK 301
312 #define SATA_A_CLK 320 #define SATA_A_CLK 302
313 #define CE3_SRC 321 #define CE3_SRC 303
314 #define CE3_CORE_CLK 322 #define CE3_CORE_CLK 304
315 #define CE3_H_CLK 323 #define CE3_H_CLK 305
316 #define USB_HS1_SYSTEM_CLK_SRC 324 #define USB_HS1_SYSTEM_CLK_SRC 306
317 #define USB_HS1_SYSTEM_CLK 325 #define USB_HS1_SYSTEM_CLK 307
318 #define EBI2_CLK 326 #define EBI2_CLK 308
319 #define EBI2_AON_CLK 327 #define EBI2_AON_CLK 309
320 328
321 #endif 329 #endif
322 330
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