1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundati 4 * Copyright (c) 2020-2021, Linaro Limited 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H 8 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H 9 10 /* GCC HW clocks */ 11 #define PCIE_0_PIPE_CLK 12 #define PCIE_1_PIPE_CLK 13 #define UFS_CARD_RX_SYMBOL_0_CLK 14 #define UFS_CARD_RX_SYMBOL_1_CLK 15 #define UFS_CARD_TX_SYMBOL_0_CLK 16 #define UFS_PHY_RX_SYMBOL_0_CLK 17 #define UFS_PHY_RX_SYMBOL_1_CLK 18 #define UFS_PHY_TX_SYMBOL_0_CLK 19 #define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 20 #define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 21 22 /* GCC clocks */ 23 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 24 #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 25 #define GCC_AGGRE_NOC_PCIE_TBU_CLK 26 #define GCC_AGGRE_UFS_CARD_AXI_CLK 27 #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 28 #define GCC_AGGRE_UFS_PHY_AXI_CLK 29 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 30 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 31 #define GCC_AGGRE_USB3_SEC_AXI_CLK 32 #define GCC_BOOT_ROM_AHB_CLK 33 #define GCC_CAMERA_HF_AXI_CLK 34 #define GCC_CAMERA_SF_AXI_CLK 35 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 36 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 37 #define GCC_DDRSS_GPU_AXI_CLK 38 #define GCC_DDRSS_PCIE_SF_TBU_CLK 39 #define GCC_DISP_HF_AXI_CLK 40 #define GCC_DISP_SF_AXI_CLK 41 #define GCC_GP1_CLK 42 #define GCC_GP1_CLK_SRC 43 #define GCC_GP2_CLK 44 #define GCC_GP2_CLK_SRC 45 #define GCC_GP3_CLK 46 #define GCC_GP3_CLK_SRC 47 #define GCC_GPLL0 48 #define GCC_GPLL0_OUT_EVEN 49 #define GCC_GPLL4 50 #define GCC_GPLL9 51 #define GCC_GPU_GPLL0_CLK_SRC 52 #define GCC_GPU_GPLL0_DIV_CLK_SRC 53 #define GCC_GPU_IREF_EN 54 #define GCC_GPU_MEMNOC_GFX_CLK 55 #define GCC_GPU_SNOC_DVM_GFX_CLK 56 #define GCC_PCIE0_PHY_RCHNG_CLK 57 #define GCC_PCIE1_PHY_RCHNG_CLK 58 #define GCC_PCIE_0_AUX_CLK 59 #define GCC_PCIE_0_AUX_CLK_SRC 60 #define GCC_PCIE_0_CFG_AHB_CLK 61 #define GCC_PCIE_0_CLKREF_EN 62 #define GCC_PCIE_0_MSTR_AXI_CLK 63 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64 #define GCC_PCIE_0_PIPE_CLK 65 #define GCC_PCIE_0_PIPE_CLK_SRC 66 #define GCC_PCIE_0_SLV_AXI_CLK 67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 68 #define GCC_PCIE_1_AUX_CLK 69 #define GCC_PCIE_1_AUX_CLK_SRC 70 #define GCC_PCIE_1_CFG_AHB_CLK 71 #define GCC_PCIE_1_CLKREF_EN 72 #define GCC_PCIE_1_MSTR_AXI_CLK 73 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 74 #define GCC_PCIE_1_PIPE_CLK 75 #define GCC_PCIE_1_PIPE_CLK_SRC 76 #define GCC_PCIE_1_SLV_AXI_CLK 77 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 78 #define GCC_PDM2_CLK 79 #define GCC_PDM2_CLK_SRC 80 #define GCC_PDM_AHB_CLK 81 #define GCC_PDM_XO4_CLK 82 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 83 #define GCC_QMIP_CAMERA_RT_AHB_CLK 84 #define GCC_QMIP_DISP_AHB_CLK 85 #define GCC_QMIP_VIDEO_CVP_AHB_CLK 86 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 87 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 88 #define GCC_QUPV3_WRAP0_CORE_CLK 89 #define GCC_QUPV3_WRAP0_S0_CLK 90 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 91 #define GCC_QUPV3_WRAP0_S1_CLK 92 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 93 #define GCC_QUPV3_WRAP0_S2_CLK 94 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 95 #define GCC_QUPV3_WRAP0_S3_CLK 96 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 97 #define GCC_QUPV3_WRAP0_S4_CLK 98 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 99 #define GCC_QUPV3_WRAP0_S5_CLK 100 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 101 #define GCC_QUPV3_WRAP0_S6_CLK 102 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 103 #define GCC_QUPV3_WRAP0_S7_CLK 104 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 105 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 106 #define GCC_QUPV3_WRAP1_CORE_CLK 107 #define GCC_QUPV3_WRAP1_S0_CLK 108 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 109 #define GCC_QUPV3_WRAP1_S1_CLK 110 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 111 #define GCC_QUPV3_WRAP1_S2_CLK 112 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 113 #define GCC_QUPV3_WRAP1_S3_CLK 114 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 115 #define GCC_QUPV3_WRAP1_S4_CLK 116 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 117 #define GCC_QUPV3_WRAP1_S5_CLK 118 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 119 #define GCC_QUPV3_WRAP2_CORE_2X_CLK 120 #define GCC_QUPV3_WRAP2_CORE_CLK 121 #define GCC_QUPV3_WRAP2_S0_CLK 122 #define GCC_QUPV3_WRAP2_S0_CLK_SRC 123 #define GCC_QUPV3_WRAP2_S1_CLK 124 #define GCC_QUPV3_WRAP2_S1_CLK_SRC 125 #define GCC_QUPV3_WRAP2_S2_CLK 126 #define GCC_QUPV3_WRAP2_S2_CLK_SRC 127 #define GCC_QUPV3_WRAP2_S3_CLK 128 #define GCC_QUPV3_WRAP2_S3_CLK_SRC 129 #define GCC_QUPV3_WRAP2_S4_CLK 130 #define GCC_QUPV3_WRAP2_S4_CLK_SRC 131 #define GCC_QUPV3_WRAP2_S5_CLK 132 #define GCC_QUPV3_WRAP2_S5_CLK_SRC 133 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 #define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 #define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 #define GCC_SDCC2_AHB_CLK 140 #define GCC_SDCC2_APPS_CLK 141 #define GCC_SDCC2_APPS_CLK_SRC 142 #define GCC_SDCC4_AHB_CLK 143 #define GCC_SDCC4_APPS_CLK 144 #define GCC_SDCC4_APPS_CLK_SRC 145 #define GCC_THROTTLE_PCIE_AHB_CLK 146 #define GCC_UFS_1_CLKREF_EN 147 #define GCC_UFS_CARD_AHB_CLK 148 #define GCC_UFS_CARD_AXI_CLK 149 #define GCC_UFS_CARD_AXI_CLK_SRC 150 #define GCC_UFS_CARD_AXI_HW_CTL_CLK 151 #define GCC_UFS_CARD_ICE_CORE_CLK 152 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153 #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 154 #define GCC_UFS_CARD_PHY_AUX_CLK 155 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 156 #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 157 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 158 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 159 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 160 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 161 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 162 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 163 #define GCC_UFS_CARD_UNIPRO_CORE_CLK 164 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 165 #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 166 #define GCC_UFS_PHY_AHB_CLK 167 #define GCC_UFS_PHY_AXI_CLK 168 #define GCC_UFS_PHY_AXI_CLK_SRC 169 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 170 #define GCC_UFS_PHY_ICE_CORE_CLK 171 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 172 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 173 #define GCC_UFS_PHY_PHY_AUX_CLK 174 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 175 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 176 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 177 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 178 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 179 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 180 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 181 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 182 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 183 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 185 #define GCC_USB30_PRIM_MASTER_CLK 186 #define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_C 187 #define GCC_USB30_PRIM_MASTER_CLK_SRC 188 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 189 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 190 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_S 191 #define GCC_USB30_PRIM_SLEEP_CLK 192 #define GCC_USB30_SEC_MASTER_CLK 193 #define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CO 194 #define GCC_USB30_SEC_MASTER_CLK_SRC 195 #define GCC_USB30_SEC_MOCK_UTMI_CLK 196 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 197 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SR 198 #define GCC_USB30_SEC_SLEEP_CLK 199 #define GCC_USB3_PRIM_PHY_AUX_CLK 200 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202 #define GCC_USB3_PRIM_PHY_PIPE_CLK 203 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204 #define GCC_USB3_SEC_CLKREF_EN 205 #define GCC_USB3_SEC_PHY_AUX_CLK 206 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 207 #define GCC_USB3_SEC_PHY_COM_AUX_CLK 208 #define GCC_USB3_SEC_PHY_PIPE_CLK 209 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 210 #define GCC_VIDEO_AXI0_CLK 211 #define GCC_VIDEO_AXI1_CLK 212 213 /* GCC resets */ 214 #define GCC_CAMERA_BCR 215 #define GCC_DISPLAY_BCR 216 #define GCC_GPU_BCR 217 #define GCC_MMSS_BCR 218 #define GCC_PCIE_0_BCR 219 #define GCC_PCIE_0_LINK_DOWN_BCR 220 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 221 #define GCC_PCIE_0_PHY_BCR 222 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 223 #define GCC_PCIE_1_BCR 224 #define GCC_PCIE_1_LINK_DOWN_BCR 225 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 226 #define GCC_PCIE_1_PHY_BCR 227 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 228 #define GCC_PCIE_PHY_CFG_AHB_BCR 229 #define GCC_PCIE_PHY_COM_BCR 230 #define GCC_PDM_BCR 231 #define GCC_QUPV3_WRAPPER_0_BCR 232 #define GCC_QUPV3_WRAPPER_1_BCR 233 #define GCC_QUPV3_WRAPPER_2_BCR 234 #define GCC_QUSB2PHY_PRIM_BCR 235 #define GCC_QUSB2PHY_SEC_BCR 236 #define GCC_SDCC2_BCR 237 #define GCC_SDCC4_BCR 238 #define GCC_UFS_CARD_BCR 239 #define GCC_UFS_PHY_BCR 240 #define GCC_USB30_PRIM_BCR 241 #define GCC_USB30_SEC_BCR 242 #define GCC_USB3_DP_PHY_PRIM_BCR 243 #define GCC_USB3_DP_PHY_SEC_BCR 244 #define GCC_USB3_PHY_PRIM_BCR 245 #define GCC_USB3_PHY_SEC_BCR 246 #define GCC_USB3PHY_PHY_PRIM_BCR 247 #define GCC_USB3PHY_PHY_SEC_BCR 248 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 249 #define GCC_VIDEO_AXI0_CLK_ARES 250 #define GCC_VIDEO_AXI1_CLK_ARES 251 #define GCC_VIDEO_BCR 252 253 /* GCC power domains */ 254 #define PCIE_0_GDSC 255 #define PCIE_1_GDSC 256 #define UFS_CARD_GDSC 257 #define UFS_PHY_GDSC 258 #define USB30_PRIM_GDSC 259 #define USB30_SEC_GDSC 260 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 261 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 262 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 263 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 264 265 #endif 266
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