1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2015, The Linux Foundation. A 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H 7 #define _DT_BINDINGS_CLK_MSM_MMCC_8996_H 8 9 #define MMPLL0_EARLY 10 #define MMPLL0_PLL 11 #define MMPLL1_EARLY 12 #define MMPLL1_PLL 13 #define MMPLL2_EARLY 14 #define MMPLL2_PLL 15 #define MMPLL3_EARLY 16 #define MMPLL3_PLL 17 #define MMPLL4_EARLY 18 #define MMPLL4_PLL 19 #define MMPLL5_EARLY 20 #define MMPLL5_PLL 21 #define MMPLL8_EARLY 22 #define MMPLL8_PLL 23 #define MMPLL9_EARLY 24 #define MMPLL9_PLL 25 #define AHB_CLK_SRC 26 #define AXI_CLK_SRC 27 #define MAXI_CLK_SRC 28 #define DSA_CORE_CLK_SRC 29 #define GFX3D_CLK_SRC 30 #define RBBMTIMER_CLK_SRC 31 #define ISENSE_CLK_SRC 32 #define RBCPR_CLK_SRC 33 #define VIDEO_CORE_CLK_SRC 34 #define VIDEO_SUBCORE0_CLK_SRC 35 #define VIDEO_SUBCORE1_CLK_SRC 36 #define PCLK0_CLK_SRC 37 #define PCLK1_CLK_SRC 38 #define MDP_CLK_SRC 39 #define EXTPCLK_CLK_SRC 40 #define VSYNC_CLK_SRC 41 #define HDMI_CLK_SRC 42 #define BYTE0_CLK_SRC 43 #define BYTE1_CLK_SRC 44 #define ESC0_CLK_SRC 45 #define ESC1_CLK_SRC 46 #define CAMSS_GP0_CLK_SRC 47 #define CAMSS_GP1_CLK_SRC 48 #define MCLK0_CLK_SRC 49 #define MCLK1_CLK_SRC 50 #define MCLK2_CLK_SRC 51 #define MCLK3_CLK_SRC 52 #define CCI_CLK_SRC 53 #define CSI0PHYTIMER_CLK_SRC 54 #define CSI1PHYTIMER_CLK_SRC 55 #define CSI2PHYTIMER_CLK_SRC 56 #define CSIPHY0_3P_CLK_SRC 57 #define CSIPHY1_3P_CLK_SRC 58 #define CSIPHY2_3P_CLK_SRC 59 #define JPEG0_CLK_SRC 60 #define JPEG2_CLK_SRC 61 #define JPEG_DMA_CLK_SRC 62 #define VFE0_CLK_SRC 63 #define VFE1_CLK_SRC 64 #define CPP_CLK_SRC 65 #define CSI0_CLK_SRC 66 #define CSI1_CLK_SRC 67 #define CSI2_CLK_SRC 68 #define CSI3_CLK_SRC 69 #define FD_CORE_CLK_SRC 70 #define MMSS_CXO_CLK 71 #define MMSS_SLEEPCLK_CLK 72 #define MMSS_MMAGIC_AHB_CLK 73 #define MMSS_MMAGIC_CFG_AHB_CLK 74 #define MMSS_MISC_AHB_CLK 75 #define MMSS_MISC_CXO_CLK 76 #define MMSS_BTO_AHB_CLK 77 #define MMSS_MMAGIC_AXI_CLK 78 #define MMSS_S0_AXI_CLK 79 #define MMSS_MMAGIC_MAXI_CLK 80 #define DSA_CORE_CLK 81 #define DSA_NOC_CFG_AHB_CLK 82 #define MMAGIC_CAMSS_AXI_CLK 83 #define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 84 #define THROTTLE_CAMSS_CXO_CLK 85 #define THROTTLE_CAMSS_AHB_CLK 86 #define THROTTLE_CAMSS_AXI_CLK 87 #define SMMU_VFE_AHB_CLK 88 #define SMMU_VFE_AXI_CLK 89 #define SMMU_CPP_AHB_CLK 90 #define SMMU_CPP_AXI_CLK 91 #define SMMU_JPEG_AHB_CLK 92 #define SMMU_JPEG_AXI_CLK 93 #define MMAGIC_MDSS_AXI_CLK 94 #define MMAGIC_MDSS_NOC_CFG_AHB_CLK 95 #define THROTTLE_MDSS_CXO_CLK 96 #define THROTTLE_MDSS_AHB_CLK 97 #define THROTTLE_MDSS_AXI_CLK 98 #define SMMU_ROT_AHB_CLK 99 #define SMMU_ROT_AXI_CLK 100 #define SMMU_MDP_AHB_CLK 101 #define SMMU_MDP_AXI_CLK 102 #define MMAGIC_VIDEO_AXI_CLK 103 #define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 104 #define THROTTLE_VIDEO_CXO_CLK 105 #define THROTTLE_VIDEO_AHB_CLK 106 #define THROTTLE_VIDEO_AXI_CLK 107 #define SMMU_VIDEO_AHB_CLK 108 #define SMMU_VIDEO_AXI_CLK 109 #define MMAGIC_BIMC_AXI_CLK 110 #define MMAGIC_BIMC_NOC_CFG_AHB_CLK 111 #define GPU_GX_GFX3D_CLK 112 #define GPU_GX_RBBMTIMER_CLK 113 #define GPU_AHB_CLK 114 #define GPU_AON_ISENSE_CLK 115 #define VMEM_MAXI_CLK 116 #define VMEM_AHB_CLK 117 #define MMSS_RBCPR_CLK 118 #define MMSS_RBCPR_AHB_CLK 119 #define VIDEO_CORE_CLK 120 #define VIDEO_AXI_CLK 121 #define VIDEO_MAXI_CLK 122 #define VIDEO_AHB_CLK 123 #define VIDEO_SUBCORE0_CLK 124 #define VIDEO_SUBCORE1_CLK 125 #define MDSS_AHB_CLK 126 #define MDSS_HDMI_AHB_CLK 127 #define MDSS_AXI_CLK 128 #define MDSS_PCLK0_CLK 129 #define MDSS_PCLK1_CLK 130 #define MDSS_MDP_CLK 131 #define MDSS_EXTPCLK_CLK 132 #define MDSS_VSYNC_CLK 133 #define MDSS_HDMI_CLK 134 #define MDSS_BYTE0_CLK 135 #define MDSS_BYTE1_CLK 136 #define MDSS_ESC0_CLK 137 #define MDSS_ESC1_CLK 138 #define CAMSS_TOP_AHB_CLK 139 #define CAMSS_AHB_CLK 140 #define CAMSS_MICRO_AHB_CLK 141 #define CAMSS_GP0_CLK 142 #define CAMSS_GP1_CLK 143 #define CAMSS_MCLK0_CLK 144 #define CAMSS_MCLK1_CLK 145 #define CAMSS_MCLK2_CLK 146 #define CAMSS_MCLK3_CLK 147 #define CAMSS_CCI_CLK 148 #define CAMSS_CCI_AHB_CLK 149 #define CAMSS_CSI0PHYTIMER_CLK 150 #define CAMSS_CSI1PHYTIMER_CLK 151 #define CAMSS_CSI2PHYTIMER_CLK 152 #define CAMSS_CSIPHY0_3P_CLK 153 #define CAMSS_CSIPHY1_3P_CLK 154 #define CAMSS_CSIPHY2_3P_CLK 155 #define CAMSS_JPEG0_CLK 156 #define CAMSS_JPEG2_CLK 157 #define CAMSS_JPEG_DMA_CLK 158 #define CAMSS_JPEG_AHB_CLK 159 #define CAMSS_JPEG_AXI_CLK 160 #define CAMSS_VFE_AHB_CLK 161 #define CAMSS_VFE_AXI_CLK 162 #define CAMSS_VFE0_CLK 163 #define CAMSS_VFE0_STREAM_CLK 164 #define CAMSS_VFE0_AHB_CLK 165 #define CAMSS_VFE1_CLK 166 #define CAMSS_VFE1_STREAM_CLK 167 #define CAMSS_VFE1_AHB_CLK 168 #define CAMSS_CSI_VFE0_CLK 169 #define CAMSS_CSI_VFE1_CLK 170 #define CAMSS_CPP_VBIF_AHB_CLK 171 #define CAMSS_CPP_AXI_CLK 172 #define CAMSS_CPP_CLK 173 #define CAMSS_CPP_AHB_CLK 174 #define CAMSS_CSI0_CLK 175 #define CAMSS_CSI0_AHB_CLK 176 #define CAMSS_CSI0PHY_CLK 177 #define CAMSS_CSI0RDI_CLK 178 #define CAMSS_CSI0PIX_CLK 179 #define CAMSS_CSI1_CLK 180 #define CAMSS_CSI1_AHB_CLK 181 #define CAMSS_CSI1PHY_CLK 182 #define CAMSS_CSI1RDI_CLK 183 #define CAMSS_CSI1PIX_CLK 184 #define CAMSS_CSI2_CLK 185 #define CAMSS_CSI2_AHB_CLK 186 #define CAMSS_CSI2PHY_CLK 187 #define CAMSS_CSI2RDI_CLK 188 #define CAMSS_CSI2PIX_CLK 189 #define CAMSS_CSI3_CLK 190 #define CAMSS_CSI3_AHB_CLK 191 #define CAMSS_CSI3PHY_CLK 192 #define CAMSS_CSI3RDI_CLK 193 #define CAMSS_CSI3PIX_CLK 194 #define CAMSS_ISPIF_AHB_CLK 195 #define FD_CORE_CLK 196 #define FD_CORE_UAR_CLK 197 #define FD_AHB_CLK 198 #define MMSS_SPDM_CSI0_CLK 199 #define MMSS_SPDM_JPEG_DMA_CLK 200 #define MMSS_SPDM_CPP_CLK 201 #define MMSS_SPDM_PCLK0_CLK 202 #define MMSS_SPDM_AHB_CLK 203 #define MMSS_SPDM_GFX3D_CLK 204 #define MMSS_SPDM_PCLK1_CLK 205 #define MMSS_SPDM_JPEG2_CLK 206 #define MMSS_SPDM_DEBUG_CLK 207 #define MMSS_SPDM_VFE1_CLK 208 #define MMSS_SPDM_VFE0_CLK 209 #define MMSS_SPDM_VIDEO_CORE_CLK 210 #define MMSS_SPDM_AXI_CLK 211 #define MMSS_SPDM_MDP_CLK 212 #define MMSS_SPDM_JPEG0_CLK 213 #define MMSS_SPDM_RM_AXI_CLK 214 #define MMSS_SPDM_RM_MAXI_CLK 215 216 #define MMAGICAHB_BCR 217 #define MMAGIC_CFG_BCR 218 #define MISC_BCR 219 #define BTO_BCR 220 #define MMAGICAXI_BCR 221 #define MMAGICMAXI_BCR 222 #define DSA_BCR 223 #define MMAGIC_CAMSS_BCR 224 #define THROTTLE_CAMSS_BCR 225 #define SMMU_VFE_BCR 226 #define SMMU_CPP_BCR 227 #define SMMU_JPEG_BCR 228 #define MMAGIC_MDSS_BCR 229 #define THROTTLE_MDSS_BCR 230 #define SMMU_ROT_BCR 231 #define SMMU_MDP_BCR 232 #define MMAGIC_VIDEO_BCR 233 #define THROTTLE_VIDEO_BCR 234 #define SMMU_VIDEO_BCR 235 #define MMAGIC_BIMC_BCR 236 #define GPU_GX_BCR 237 #define GPU_BCR 238 #define GPU_AON_BCR 239 #define VMEM_BCR 240 #define MMSS_RBCPR_BCR 241 #define VIDEO_BCR 242 #define MDSS_BCR 243 #define CAMSS_TOP_BCR 244 #define CAMSS_AHB_BCR 245 #define CAMSS_MICRO_BCR 246 #define CAMSS_CCI_BCR 247 #define CAMSS_PHY0_BCR 248 #define CAMSS_PHY1_BCR 249 #define CAMSS_PHY2_BCR 250 #define CAMSS_CSIPHY0_3P_BCR 251 #define CAMSS_CSIPHY1_3P_BCR 252 #define CAMSS_CSIPHY2_3P_BCR 253 #define CAMSS_JPEG_BCR 254 #define CAMSS_VFE_BCR 255 #define CAMSS_VFE0_BCR 256 #define CAMSS_VFE1_BCR 257 #define CAMSS_CSI_VFE0_BCR 258 #define CAMSS_CSI_VFE1_BCR 259 #define CAMSS_CPP_TOP_BCR 260 #define CAMSS_CPP_BCR 261 #define CAMSS_CSI0_BCR 262 #define CAMSS_CSI0RDI_BCR 263 #define CAMSS_CSI0PIX_BCR 264 #define CAMSS_CSI1_BCR 265 #define CAMSS_CSI1RDI_BCR 266 #define CAMSS_CSI1PIX_BCR 267 #define CAMSS_CSI2_BCR 268 #define CAMSS_CSI2RDI_BCR 269 #define CAMSS_CSI2PIX_BCR 270 #define CAMSS_CSI3_BCR 271 #define CAMSS_CSI3RDI_BCR 272 #define CAMSS_CSI3PIX_BCR 273 #define CAMSS_ISPIF_BCR 274 #define FD_BCR 275 #define MMSS_SPDM_RM_BCR 276 277 /* Indexes for GDSCs */ 278 #define MMAGIC_VIDEO_GDSC 0 279 #define MMAGIC_MDSS_GDSC 1 280 #define MMAGIC_CAMSS_GDSC 2 281 #define GPU_GDSC 3 282 #define VENUS_GDSC 4 283 #define VENUS_CORE0_GDSC 5 284 #define VENUS_CORE1_GDSC 6 285 #define CAMSS_GDSC 7 286 #define VFE0_GDSC 8 287 #define VFE1_GDSC 9 288 #define JPEG_GDSC 10 289 #define CPP_GDSC 11 290 #define FD_GDSC 12 291 #define MDSS_GDSC 13 292 #define GPU_GX_GDSC 14 293 #define MMAGIC_BIMC_GDSC 15 294 295 #endif 296
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