1 /* SPDX-License-Identifier: GPL-2.0-only OR BS 1 2 /* 3 * Copyright (c) 2021-2023, Qualcomm Innovatio 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H 7 #define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H 8 9 /* GCC clocks */ 10 #define GCC_GPLL0 11 #define GCC_GPLL0_OUT_EVEN 12 #define GCC_GPLL1 13 #define GCC_GPLL2 14 #define GCC_GPLL2_OUT_EVEN 15 #define GCC_GPLL3 16 #define GCC_GPLL4 17 #define GCC_GPLL5 18 #define GCC_GPLL5_OUT_EVEN 19 #define GCC_GPLL6 20 #define GCC_GPLL7 21 #define GCC_GPLL8 22 #define GCC_AGGRE_NOC_ECPRI_DMA_CLK 23 #define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 24 #define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 25 #define GCC_BOOT_ROM_AHB_CLK 26 #define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 27 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 28 #define GCC_DDRSS_ECPRI_DMA_CLK 29 #define GCC_ECPRI_AHB_CLK 30 #define GCC_ECPRI_CC_GPLL0_CLK_SRC 31 #define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 32 #define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 33 #define GCC_ECPRI_CC_GPLL3_CLK_SRC 34 #define GCC_ECPRI_CC_GPLL4_CLK_SRC 35 #define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 36 #define GCC_ECPRI_XO_CLK 37 #define GCC_ETH_DBG_SNOC_AXI_CLK 38 #define GCC_GEMNOC_PCIE_QX_CLK 39 #define GCC_GP1_CLK 40 #define GCC_GP1_CLK_SRC 41 #define GCC_GP2_CLK 42 #define GCC_GP2_CLK_SRC 43 #define GCC_GP3_CLK 44 #define GCC_GP3_CLK_SRC 45 #define GCC_PCIE_0_AUX_CLK 46 #define GCC_PCIE_0_AUX_CLK_SRC 47 #define GCC_PCIE_0_CFG_AHB_CLK 48 #define GCC_PCIE_0_CLKREF_EN 49 #define GCC_PCIE_0_MSTR_AXI_CLK 50 #define GCC_PCIE_0_PHY_AUX_CLK 51 #define GCC_PCIE_0_PHY_RCHNG_CLK 52 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 #define GCC_PCIE_0_PIPE_CLK 54 #define GCC_PCIE_0_SLV_AXI_CLK 55 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 #define GCC_PDM2_CLK 57 #define GCC_PDM2_CLK_SRC 58 #define GCC_PDM_AHB_CLK 59 #define GCC_PDM_XO4_CLK 60 #define GCC_QMIP_ANOC_PCIE_CLK 61 #define GCC_QMIP_ECPRI_DMA0_CLK 62 #define GCC_QMIP_ECPRI_DMA1_CLK 63 #define GCC_QMIP_ECPRI_GSI_CLK 64 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 65 #define GCC_QUPV3_WRAP0_CORE_CLK 66 #define GCC_QUPV3_WRAP0_S0_CLK 67 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 68 #define GCC_QUPV3_WRAP0_S1_CLK 69 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 70 #define GCC_QUPV3_WRAP0_S2_CLK 71 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 72 #define GCC_QUPV3_WRAP0_S3_CLK 73 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 74 #define GCC_QUPV3_WRAP0_S4_CLK 75 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 76 #define GCC_QUPV3_WRAP0_S5_CLK 77 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 78 #define GCC_QUPV3_WRAP0_S6_CLK 79 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 80 #define GCC_QUPV3_WRAP0_S7_CLK 81 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 82 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 83 #define GCC_QUPV3_WRAP1_CORE_CLK 84 #define GCC_QUPV3_WRAP1_S0_CLK 85 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 86 #define GCC_QUPV3_WRAP1_S1_CLK 87 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 88 #define GCC_QUPV3_WRAP1_S2_CLK 89 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 90 #define GCC_QUPV3_WRAP1_S3_CLK 91 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 92 #define GCC_QUPV3_WRAP1_S4_CLK 93 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 94 #define GCC_QUPV3_WRAP1_S5_CLK 95 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 96 #define GCC_QUPV3_WRAP1_S6_CLK 97 #define GCC_QUPV3_WRAP1_S6_CLK_SRC 98 #define GCC_QUPV3_WRAP1_S7_CLK 99 #define GCC_QUPV3_WRAP1_S7_CLK_SRC 100 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 101 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 102 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 103 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 104 #define GCC_SDCC5_AHB_CLK 105 #define GCC_SDCC5_APPS_CLK 106 #define GCC_SDCC5_APPS_CLK_SRC 107 #define GCC_SDCC5_ICE_CORE_CLK 108 #define GCC_SDCC5_ICE_CORE_CLK_SRC 109 #define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 110 #define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 111 #define GCC_SNOC_CNOC_PCIE_QX_CLK 112 #define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 113 #define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 114 #define GCC_TSC_CFG_AHB_CLK 115 #define GCC_TSC_CLK_SRC 116 #define GCC_TSC_CNTR_CLK 117 #define GCC_TSC_ETU_CLK 118 #define GCC_USB2_CLKREF_EN 119 #define GCC_USB30_PRIM_MASTER_CLK 120 #define GCC_USB30_PRIM_MASTER_CLK_SRC 121 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 122 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 123 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_S 124 #define GCC_USB30_PRIM_SLEEP_CLK 125 #define GCC_USB3_PRIM_PHY_AUX_CLK 126 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 127 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 128 #define GCC_USB3_PRIM_PHY_PIPE_CLK 129 #define GCC_SM_BUS_AHB_CLK 130 #define GCC_SM_BUS_XO_CLK 131 #define GCC_SM_BUS_XO_CLK_SRC 132 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 133 #define GCC_ETH_100G_C2C_HM_APB_CLK 134 #define GCC_ETH_100G_FH_HM_APB_0_CLK 135 #define GCC_ETH_100G_FH_HM_APB_1_CLK 136 #define GCC_ETH_100G_FH_HM_APB_2_CLK 137 #define GCC_ETH_DBG_C2C_HM_APB_CLK 138 #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 139 #define GCC_PCIE_0_PIPE_CLK_SRC 140 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 141 #define GCC_GPLL1_OUT_EVEN 142 #define GCC_DDRSS_ECPRI_GSI_CLK 143 144 /* GCC resets */ 145 #define GCC_ECPRI_CC_BCR 146 #define GCC_ECPRI_SS_BCR 147 #define GCC_ETH_WRAPPER_BCR 148 #define GCC_PCIE_0_BCR 149 #define GCC_PCIE_0_LINK_DOWN_BCR 150 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 151 #define GCC_PCIE_0_PHY_BCR 152 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 153 #define GCC_PCIE_PHY_CFG_AHB_BCR 154 #define GCC_PCIE_PHY_COM_BCR 155 #define GCC_PDM_BCR 156 #define GCC_QUPV3_WRAPPER_0_BCR 157 #define GCC_QUPV3_WRAPPER_1_BCR 158 #define GCC_QUSB2PHY_PRIM_BCR 159 #define GCC_QUSB2PHY_SEC_BCR 160 #define GCC_SDCC5_BCR 161 #define GCC_TCSR_PCIE_BCR 162 #define GCC_TSC_BCR 163 #define GCC_USB30_PRIM_BCR 164 #define GCC_USB3_DP_PHY_PRIM_BCR 165 #define GCC_USB3_DP_PHY_SEC_BCR 166 #define GCC_USB3_PHY_PRIM_BCR 167 #define GCC_USB3_PHY_SEC_BCR 168 #define GCC_USB3PHY_PHY_PRIM_BCR 169 #define GCC_USB3PHY_PHY_SEC_BCR 170 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 171 172 /* GCC power domains */ 173 #define PCIE_0_GDSC 174 #define PCIE_0_PHY_GDSC 175 #define USB30_PRIM_GDSC 176 177 #endif 178
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