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Linux/include/dt-bindings/clock/qcom,sm4450-dispcc.h

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Diff markup

Differences between /include/dt-bindings/clock/qcom,sm4450-dispcc.h (Version linux-6.12-rc7) and /include/dt-bindings/clock/qcom,sm4450-dispcc.h (Version linux-5.0.21)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR B      1 
  2 /*                                                
  3  * Copyright (c) 2024, Qualcomm Innovation Cen    
  4  */                                               
  5                                                   
  6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H    
  7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H    
  8                                                   
  9 /* DISP_CC clocks */                              
 10 #define DISP_CC_MDSS_AHB1_CLK                     
 11 #define DISP_CC_MDSS_AHB_CLK                      
 12 #define DISP_CC_MDSS_AHB_CLK_SRC                  
 13 #define DISP_CC_MDSS_BYTE0_CLK                    
 14 #define DISP_CC_MDSS_BYTE0_CLK_SRC                
 15 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC            
 16 #define DISP_CC_MDSS_BYTE0_INTF_CLK               
 17 #define DISP_CC_MDSS_ESC0_CLK                     
 18 #define DISP_CC_MDSS_ESC0_CLK_SRC                 
 19 #define DISP_CC_MDSS_MDP1_CLK                     
 20 #define DISP_CC_MDSS_MDP_CLK                      
 21 #define DISP_CC_MDSS_MDP_CLK_SRC                  
 22 #define DISP_CC_MDSS_MDP_LUT1_CLK                 
 23 #define DISP_CC_MDSS_MDP_LUT_CLK                  
 24 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK             
 25 #define DISP_CC_MDSS_PCLK0_CLK                    
 26 #define DISP_CC_MDSS_PCLK0_CLK_SRC                
 27 #define DISP_CC_MDSS_ROT1_CLK                     
 28 #define DISP_CC_MDSS_ROT_CLK                      
 29 #define DISP_CC_MDSS_ROT_CLK_SRC                  
 30 #define DISP_CC_MDSS_RSCC_AHB_CLK                 
 31 #define DISP_CC_MDSS_RSCC_VSYNC_CLK               
 32 #define DISP_CC_MDSS_VSYNC1_CLK                   
 33 #define DISP_CC_MDSS_VSYNC_CLK                    
 34 #define DISP_CC_MDSS_VSYNC_CLK_SRC                
 35 #define DISP_CC_PLL0                              
 36 #define DISP_CC_PLL1                              
 37 #define DISP_CC_SLEEP_CLK                         
 38 #define DISP_CC_SLEEP_CLK_SRC                     
 39 #define DISP_CC_XO_CLK                            
 40 #define DISP_CC_XO_CLK_SRC                        
 41                                                   
 42 /* DISP_CC power domains */                       
 43 #define DISP_CC_MDSS_CORE_GDSC                    
 44 #define DISP_CC_MDSS_CORE_INT2_GDSC               
 45                                                   
 46 /* DISP_CC resets */                              
 47 #define DISP_CC_MDSS_CORE_BCR                     
 48 #define DISP_CC_MDSS_CORE_INT2_BCR                
 49 #define DISP_CC_MDSS_RSCC_BCR                     
 50                                                   
 51 #endif                                            
 52                                                   

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