1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Cen 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H 7 #define _DT_BINDINGS_CLK_QCOM_GCC_SM4450_H 8 9 /* GCC clocks */ 10 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11 #define GCC_AGGRE_UFS_PHY_AXI_CLK 12 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 13 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 14 #define GCC_BOOT_ROM_AHB_CLK 15 #define GCC_CAMERA_AHB_CLK 16 #define GCC_CAMERA_HF_AXI_CLK 17 #define GCC_CAMERA_SF_AXI_CLK 18 #define GCC_CAMERA_SLEEP_CLK 19 #define GCC_CAMERA_XO_CLK 20 #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 21 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 22 #define GCC_DDRSS_GPU_AXI_CLK 23 #define GCC_DDRSS_PCIE_SF_TBU_CLK 24 #define GCC_DISP_AHB_CLK 25 #define GCC_DISP_HF_AXI_CLK 26 #define GCC_DISP_XO_CLK 27 #define GCC_EUSB3_0_CLKREF_EN 28 #define GCC_GP1_CLK 29 #define GCC_GP1_CLK_SRC 30 #define GCC_GP2_CLK 31 #define GCC_GP2_CLK_SRC 32 #define GCC_GP3_CLK 33 #define GCC_GP3_CLK_SRC 34 #define GCC_GPLL0 35 #define GCC_GPLL0_OUT_EVEN 36 #define GCC_GPLL0_OUT_ODD 37 #define GCC_GPLL1 38 #define GCC_GPLL3 39 #define GCC_GPLL4 40 #define GCC_GPLL9 41 #define GCC_GPLL10 42 #define GCC_GPU_CFG_AHB_CLK 43 #define GCC_GPU_GPLL0_CLK_SRC 44 #define GCC_GPU_GPLL0_DIV_CLK_SRC 45 #define GCC_GPU_MEMNOC_GFX_CLK 46 #define GCC_GPU_SNOC_DVM_GFX_CLK 47 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU 48 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_ 49 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK 50 #define GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK 51 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK 52 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK 53 #define GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK 54 #define GCC_HLOS1_VOTE_MMU_TCU_CLK 55 #define GCC_PCIE_0_AUX_CLK 56 #define GCC_PCIE_0_AUX_CLK_SRC 57 #define GCC_PCIE_0_CFG_AHB_CLK 58 #define GCC_PCIE_0_CLKREF_EN 59 #define GCC_PCIE_0_MSTR_AXI_CLK 60 #define GCC_PCIE_0_PHY_RCHNG_CLK 61 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 62 #define GCC_PCIE_0_PIPE_CLK 63 #define GCC_PCIE_0_PIPE_CLK_SRC 64 #define GCC_PCIE_0_PIPE_DIV2_CLK 65 #define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 66 #define GCC_PCIE_0_SLV_AXI_CLK 67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 68 #define GCC_PDM2_CLK 69 #define GCC_PDM2_CLK_SRC 70 #define GCC_PDM_AHB_CLK 71 #define GCC_PDM_XO4_CLK 72 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 73 #define GCC_QMIP_CAMERA_RT_AHB_CLK 74 #define GCC_QMIP_DISP_AHB_CLK 75 #define GCC_QMIP_GPU_AHB_CLK 76 #define GCC_QMIP_PCIE_AHB_CLK 77 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 78 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 79 #define GCC_QUPV3_WRAP0_CORE_CLK 80 #define GCC_QUPV3_WRAP0_S0_CLK 81 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 82 #define GCC_QUPV3_WRAP0_S1_CLK 83 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 84 #define GCC_QUPV3_WRAP0_S2_CLK 85 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 86 #define GCC_QUPV3_WRAP0_S3_CLK 87 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 88 #define GCC_QUPV3_WRAP0_S4_CLK 89 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 90 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 91 #define GCC_QUPV3_WRAP1_CORE_CLK 92 #define GCC_QUPV3_WRAP1_S0_CLK 93 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 94 #define GCC_QUPV3_WRAP1_S1_CLK 95 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 96 #define GCC_QUPV3_WRAP1_S2_CLK 97 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 98 #define GCC_QUPV3_WRAP1_S3_CLK 99 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 100 #define GCC_QUPV3_WRAP1_S4_CLK 101 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 102 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 103 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 104 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 105 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 106 #define GCC_SDCC1_AHB_CLK 107 #define GCC_SDCC1_APPS_CLK 108 #define GCC_SDCC1_APPS_CLK_SRC 109 #define GCC_SDCC1_ICE_CORE_CLK 110 #define GCC_SDCC1_ICE_CORE_CLK_SRC 111 #define GCC_SDCC2_AHB_CLK 112 #define GCC_SDCC2_APPS_CLK 113 #define GCC_SDCC2_APPS_CLK_SRC 114 #define GCC_UFS_0_CLKREF_EN 115 #define GCC_UFS_PAD_CLKREF_EN 116 #define GCC_UFS_PHY_AHB_CLK 117 #define GCC_UFS_PHY_AXI_CLK 118 #define GCC_UFS_PHY_AXI_CLK_SRC 119 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 120 #define GCC_UFS_PHY_ICE_CORE_CLK 121 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 122 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 123 #define GCC_UFS_PHY_PHY_AUX_CLK 124 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 125 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 126 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 127 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 128 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 129 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 130 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 131 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 132 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 133 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 134 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 135 #define GCC_USB30_PRIM_MASTER_CLK 136 #define GCC_USB30_PRIM_MASTER_CLK_SRC 137 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 138 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 139 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_S 140 #define GCC_USB30_PRIM_SLEEP_CLK 141 #define GCC_USB3_0_CLKREF_EN 142 #define GCC_USB3_PRIM_PHY_AUX_CLK 143 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145 #define GCC_USB3_PRIM_PHY_PIPE_CLK 146 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147 #define GCC_VCODEC0_AXI_CLK 148 #define GCC_VENUS_CTL_AXI_CLK 149 #define GCC_VIDEO_AHB_CLK 150 #define GCC_VIDEO_THROTTLE_CORE_CLK 151 #define GCC_VIDEO_VCODEC0_SYS_CLK 152 #define GCC_VIDEO_VENUS_CLK_SRC 153 #define GCC_VIDEO_VENUS_CTL_CLK 154 #define GCC_VIDEO_XO_CLK 155 156 /* GCC power domains */ 157 #define GCC_PCIE_0_GDSC 158 #define GCC_UFS_PHY_GDSC 159 #define GCC_USB30_PRIM_GDSC 160 #define GCC_VCODEC0_GDSC 161 #define GCC_VENUS_GDSC 162 163 /* GCC resets */ 164 #define GCC_CAMERA_BCR 165 #define GCC_DISPLAY_BCR 166 #define GCC_GPU_BCR 167 #define GCC_PCIE_0_BCR 168 #define GCC_PCIE_0_LINK_DOWN_BCR 169 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 170 #define GCC_PCIE_0_PHY_BCR 171 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 172 #define GCC_PCIE_PHY_BCR 173 #define GCC_PCIE_PHY_CFG_AHB_BCR 174 #define GCC_PCIE_PHY_COM_BCR 175 #define GCC_PDM_BCR 176 #define GCC_QUPV3_WRAPPER_0_BCR 177 #define GCC_QUPV3_WRAPPER_1_BCR 178 #define GCC_QUSB2PHY_PRIM_BCR 179 #define GCC_QUSB2PHY_SEC_BCR 180 #define GCC_SDCC1_BCR 181 #define GCC_SDCC2_BCR 182 #define GCC_UFS_PHY_BCR 183 #define GCC_USB30_PRIM_BCR 184 #define GCC_USB3_DP_PHY_PRIM_BCR 185 #define GCC_USB3_DP_PHY_SEC_BCR 186 #define GCC_USB3_PHY_PRIM_BCR 187 #define GCC_USB3_PHY_SEC_BCR 188 #define GCC_USB3PHY_PHY_PRIM_BCR 189 #define GCC_USB3PHY_PHY_SEC_BCR 190 #define GCC_VCODEC0_BCR 191 #define GCC_VENUS_BCR 192 #define GCC_VIDEO_BCR 193 #define GCC_VIDEO_VENUS_BCR 194 #define GCC_VENUS_CTL_AXI_CLK_ARES 195 #define GCC_VIDEO_VENUS_CTL_CLK_ARES 196 197 #endif 198
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