1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Cen 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H 6 #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H 7 #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H 7 #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H 8 8 9 /* GPU_CC clocks */ 9 /* GPU_CC clocks */ 10 #define GPU_CC_AHB_CLK 10 #define GPU_CC_AHB_CLK 0 11 #define GPU_CC_CB_CLK 11 #define GPU_CC_CB_CLK 1 12 #define GPU_CC_CRC_AHB_CLK 12 #define GPU_CC_CRC_AHB_CLK 2 13 #define GPU_CC_CX_FF_CLK 13 #define GPU_CC_CX_FF_CLK 3 14 #define GPU_CC_CX_GFX3D_CLK 14 #define GPU_CC_CX_GFX3D_CLK 4 15 #define GPU_CC_CX_GFX3D_SLV_CLK 15 #define GPU_CC_CX_GFX3D_SLV_CLK 5 16 #define GPU_CC_CX_GMU_CLK 16 #define GPU_CC_CX_GMU_CLK 6 17 #define GPU_CC_CX_SNOC_DVM_CLK 17 #define GPU_CC_CX_SNOC_DVM_CLK 7 18 #define GPU_CC_CXO_AON_CLK 18 #define GPU_CC_CXO_AON_CLK 8 19 #define GPU_CC_CXO_CLK 19 #define GPU_CC_CXO_CLK 9 20 #define GPU_CC_DEMET_CLK 20 #define GPU_CC_DEMET_CLK 10 21 #define GPU_CC_DEMET_DIV_CLK_SRC 21 #define GPU_CC_DEMET_DIV_CLK_SRC 11 22 #define GPU_CC_FF_CLK_SRC 22 #define GPU_CC_FF_CLK_SRC 12 23 #define GPU_CC_FREQ_MEASURE_CLK 23 #define GPU_CC_FREQ_MEASURE_CLK 13 24 #define GPU_CC_GMU_CLK_SRC 24 #define GPU_CC_GMU_CLK_SRC 14 25 #define GPU_CC_GX_CXO_CLK 25 #define GPU_CC_GX_CXO_CLK 15 26 #define GPU_CC_GX_FF_CLK 26 #define GPU_CC_GX_FF_CLK 16 27 #define GPU_CC_GX_GFX3D_CLK 27 #define GPU_CC_GX_GFX3D_CLK 17 28 #define GPU_CC_GX_GFX3D_CLK_SRC 28 #define GPU_CC_GX_GFX3D_CLK_SRC 18 29 #define GPU_CC_GX_GFX3D_RDVM_CLK 29 #define GPU_CC_GX_GFX3D_RDVM_CLK 19 30 #define GPU_CC_GX_GMU_CLK 30 #define GPU_CC_GX_GMU_CLK 20 31 #define GPU_CC_GX_VSENSE_CLK 31 #define GPU_CC_GX_VSENSE_CLK 21 32 #define GPU_CC_HUB_AHB_DIV_CLK_SRC 32 #define GPU_CC_HUB_AHB_DIV_CLK_SRC 22 33 #define GPU_CC_HUB_AON_CLK 33 #define GPU_CC_HUB_AON_CLK 23 34 #define GPU_CC_HUB_CLK_SRC 34 #define GPU_CC_HUB_CLK_SRC 24 35 #define GPU_CC_HUB_CX_INT_CLK 35 #define GPU_CC_HUB_CX_INT_CLK 25 36 #define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 36 #define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26 37 #define GPU_CC_MEMNOC_GFX_CLK 37 #define GPU_CC_MEMNOC_GFX_CLK 27 38 #define GPU_CC_MND1X_0_GFX3D_CLK 38 #define GPU_CC_MND1X_0_GFX3D_CLK 28 39 #define GPU_CC_PLL0 39 #define GPU_CC_PLL0 29 40 #define GPU_CC_PLL1 40 #define GPU_CC_PLL1 30 41 #define GPU_CC_SLEEP_CLK 41 #define GPU_CC_SLEEP_CLK 31 42 #define GPU_CC_XO_CLK_SRC 42 #define GPU_CC_XO_CLK_SRC 32 43 #define GPU_CC_XO_DIV_CLK_SRC 43 #define GPU_CC_XO_DIV_CLK_SRC 33 44 44 45 /* GPU_CC power domains */ 45 /* GPU_CC power domains */ 46 #define GPU_CC_CX_GDSC 46 #define GPU_CC_CX_GDSC 0 47 #define GPU_CC_GX_GDSC 47 #define GPU_CC_GX_GDSC 1 48 48 49 /* GPU_CC resets */ 49 /* GPU_CC resets */ 50 #define GPU_CC_ACD_BCR 50 #define GPU_CC_ACD_BCR 0 51 #define GPU_CC_CB_BCR 51 #define GPU_CC_CB_BCR 1 52 #define GPU_CC_CX_BCR 52 #define GPU_CC_CX_BCR 2 53 #define GPU_CC_FAST_HUB_BCR 53 #define GPU_CC_FAST_HUB_BCR 3 54 #define GPU_CC_FF_BCR 54 #define GPU_CC_FF_BCR 4 55 #define GPU_CC_GFX3D_AON_BCR 55 #define GPU_CC_GFX3D_AON_BCR 5 56 #define GPU_CC_GMU_BCR 56 #define GPU_CC_GMU_BCR 6 57 #define GPU_CC_GX_BCR 57 #define GPU_CC_GX_BCR 7 58 #define GPU_CC_XO_BCR 58 #define GPU_CC_XO_BCR 8 59 #define GPU_CC_GX_ACD_IROOT_BCR 59 #define GPU_CC_GX_ACD_IROOT_BCR 9 60 #define GPU_CC_RBCPR_BCR 60 #define GPU_CC_RBCPR_BCR 10 61 61 62 #endif 62 #endif 63 63
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