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Linux/include/dt-bindings/clock/qcom,sm6115-dispcc.h

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Diff markup

Differences between /include/dt-bindings/clock/qcom,sm6115-dispcc.h (Architecture ppc) and /include/dt-bindings/clock/qcom,sm6115-dispcc.h (Architecture m68k)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR B      1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*                                                  2 /*
  3  * Copyright (c) 2022, The Linux Foundation. A      3  * Copyright (c) 2022, The Linux Foundation. All rights reserved.
  4  */                                                 4  */
  5                                                     5 
  6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H      6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
  7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H      7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
  8                                                     8 
  9 /* DISP_CC clocks */                                9 /* DISP_CC clocks */
 10 #define DISP_CC_PLL0                    0          10 #define DISP_CC_PLL0                    0
 11 #define DISP_CC_PLL0_OUT_MAIN           1          11 #define DISP_CC_PLL0_OUT_MAIN           1
 12 #define DISP_CC_MDSS_AHB_CLK            2          12 #define DISP_CC_MDSS_AHB_CLK            2
 13 #define DISP_CC_MDSS_AHB_CLK_SRC        3          13 #define DISP_CC_MDSS_AHB_CLK_SRC        3
 14 #define DISP_CC_MDSS_BYTE0_CLK          4          14 #define DISP_CC_MDSS_BYTE0_CLK          4
 15 #define DISP_CC_MDSS_BYTE0_CLK_SRC      5          15 #define DISP_CC_MDSS_BYTE0_CLK_SRC      5
 16 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC  6          16 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC  6
 17 #define DISP_CC_MDSS_BYTE0_INTF_CLK     7          17 #define DISP_CC_MDSS_BYTE0_INTF_CLK     7
 18 #define DISP_CC_MDSS_ESC0_CLK           8          18 #define DISP_CC_MDSS_ESC0_CLK           8
 19 #define DISP_CC_MDSS_ESC0_CLK_SRC       9          19 #define DISP_CC_MDSS_ESC0_CLK_SRC       9
 20 #define DISP_CC_MDSS_MDP_CLK            10         20 #define DISP_CC_MDSS_MDP_CLK            10
 21 #define DISP_CC_MDSS_MDP_CLK_SRC        11         21 #define DISP_CC_MDSS_MDP_CLK_SRC        11
 22 #define DISP_CC_MDSS_MDP_LUT_CLK        12         22 #define DISP_CC_MDSS_MDP_LUT_CLK        12
 23 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK   13         23 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK   13
 24 #define DISP_CC_MDSS_PCLK0_CLK          14         24 #define DISP_CC_MDSS_PCLK0_CLK          14
 25 #define DISP_CC_MDSS_PCLK0_CLK_SRC      15         25 #define DISP_CC_MDSS_PCLK0_CLK_SRC      15
 26 #define DISP_CC_MDSS_ROT_CLK            16         26 #define DISP_CC_MDSS_ROT_CLK            16
 27 #define DISP_CC_MDSS_ROT_CLK_SRC        17         27 #define DISP_CC_MDSS_ROT_CLK_SRC        17
 28 #define DISP_CC_MDSS_VSYNC_CLK          18         28 #define DISP_CC_MDSS_VSYNC_CLK          18
 29 #define DISP_CC_MDSS_VSYNC_CLK_SRC      19         29 #define DISP_CC_MDSS_VSYNC_CLK_SRC      19
 30 #define DISP_CC_SLEEP_CLK               20         30 #define DISP_CC_SLEEP_CLK               20
 31 #define DISP_CC_SLEEP_CLK_SRC           21         31 #define DISP_CC_SLEEP_CLK_SRC           21
 32                                                    32 
 33 /* DISP_CC GDSCR */                                33 /* DISP_CC GDSCR */
 34 #define MDSS_GDSC                       0          34 #define MDSS_GDSC                       0
 35                                                    35 
 36 #endif                                             36 #endif
 37                                                    37 

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