1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2018, The Linux Foundation. A 4 * Copyright (c) 2024, Danila Tikhonov <danila 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H 8 #define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H 9 10 /* Hardware clocks */ 11 #define CAMCC_PLL0_OUT_EVEN 12 #define CAMCC_PLL0_OUT_ODD 13 #define CAMCC_PLL1_OUT_EVEN 14 #define CAMCC_PLL2_OUT_EARLY 15 #define CAMCC_PLL3_OUT_EVEN 16 #define CAMCC_PLL4_OUT_EVEN 17 18 /* CAMCC clock registers */ 19 #define CAMCC_PLL0 20 #define CAMCC_PLL1 21 #define CAMCC_PLL2 22 #define CAMCC_PLL2_OUT_AUX 23 #define CAMCC_PLL2_OUT_MAIN 24 #define CAMCC_PLL3 25 #define CAMCC_PLL4 26 #define CAMCC_BPS_AHB_CLK 27 #define CAMCC_BPS_AREG_CLK 28 #define CAMCC_BPS_AXI_CLK 29 #define CAMCC_BPS_CLK 30 #define CAMCC_BPS_CLK_SRC 31 #define CAMCC_CAMNOC_AXI_CLK 32 #define CAMCC_CAMNOC_AXI_CLK_SRC 33 #define CAMCC_CAMNOC_DCD_XO_CLK 34 #define CAMCC_CCI_0_CLK 35 #define CAMCC_CCI_0_CLK_SRC 36 #define CAMCC_CCI_1_CLK 37 #define CAMCC_CCI_1_CLK_SRC 38 #define CAMCC_CORE_AHB_CLK 39 #define CAMCC_CPAS_AHB_CLK 40 #define CAMCC_CPHY_RX_CLK_SRC 41 #define CAMCC_CSI0PHYTIMER_CLK 42 #define CAMCC_CSI0PHYTIMER_CLK_SRC 43 #define CAMCC_CSI1PHYTIMER_CLK 44 #define CAMCC_CSI1PHYTIMER_CLK_SRC 45 #define CAMCC_CSI2PHYTIMER_CLK 46 #define CAMCC_CSI2PHYTIMER_CLK_SRC 47 #define CAMCC_CSI3PHYTIMER_CLK 48 #define CAMCC_CSI3PHYTIMER_CLK_SRC 49 #define CAMCC_CSIPHY0_CLK 50 #define CAMCC_CSIPHY1_CLK 51 #define CAMCC_CSIPHY2_CLK 52 #define CAMCC_CSIPHY3_CLK 53 #define CAMCC_FAST_AHB_CLK_SRC 54 #define CAMCC_FD_CORE_CLK 55 #define CAMCC_FD_CORE_CLK_SRC 56 #define CAMCC_FD_CORE_UAR_CLK 57 #define CAMCC_ICP_AHB_CLK 58 #define CAMCC_ICP_CLK 59 #define CAMCC_ICP_CLK_SRC 60 #define CAMCC_IFE_0_AXI_CLK 61 #define CAMCC_IFE_0_CLK 62 #define CAMCC_IFE_0_CLK_SRC 63 #define CAMCC_IFE_0_CPHY_RX_CLK 64 #define CAMCC_IFE_0_CSID_CLK 65 #define CAMCC_IFE_0_CSID_CLK_SRC 66 #define CAMCC_IFE_0_DSP_CLK 67 #define CAMCC_IFE_1_AXI_CLK 68 #define CAMCC_IFE_1_CLK 69 #define CAMCC_IFE_1_CLK_SRC 70 #define CAMCC_IFE_1_CPHY_RX_CLK 71 #define CAMCC_IFE_1_CSID_CLK 72 #define CAMCC_IFE_1_CSID_CLK_SRC 73 #define CAMCC_IFE_1_DSP_CLK 74 #define CAMCC_IFE_LITE_CLK 75 #define CAMCC_IFE_LITE_CLK_SRC 76 #define CAMCC_IFE_LITE_CPHY_RX_CLK 77 #define CAMCC_IFE_LITE_CSID_CLK 78 #define CAMCC_IFE_LITE_CSID_CLK_SRC 79 #define CAMCC_IPE_0_AHB_CLK 80 #define CAMCC_IPE_0_AREG_CLK 81 #define CAMCC_IPE_0_AXI_CLK 82 #define CAMCC_IPE_0_CLK 83 #define CAMCC_IPE_0_CLK_SRC 84 #define CAMCC_IPE_1_AHB_CLK 85 #define CAMCC_IPE_1_AREG_CLK 86 #define CAMCC_IPE_1_AXI_CLK 87 #define CAMCC_IPE_1_CLK 88 #define CAMCC_JPEG_CLK 89 #define CAMCC_JPEG_CLK_SRC 90 #define CAMCC_LRME_CLK 91 #define CAMCC_LRME_CLK_SRC 92 #define CAMCC_MCLK0_CLK 93 #define CAMCC_MCLK0_CLK_SRC 94 #define CAMCC_MCLK1_CLK 95 #define CAMCC_MCLK1_CLK_SRC 96 #define CAMCC_MCLK2_CLK 97 #define CAMCC_MCLK2_CLK_SRC 98 #define CAMCC_MCLK3_CLK 99 #define CAMCC_MCLK3_CLK_SRC 100 #define CAMCC_SLEEP_CLK 101 #define CAMCC_SLEEP_CLK_SRC 102 #define CAMCC_SLOW_AHB_CLK_SRC 103 #define CAMCC_XO_CLK_SRC 104 105 /* CAMCC GDSCRs */ 106 #define BPS_GDSC 107 #define IFE_0_GDSC 108 #define IFE_1_GDSC 109 #define IPE_0_GDSC 110 #define IPE_1_GDSC 111 #define TITAN_TOP_GDSC 112 113 #endif 114
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