1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2018, The Linux Foundation. A 4 * Copyright (c) 2024, Danila Tikhonov <danila 5 * Copyright (c) 2024, David Wronek <david@mai 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 9 #define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 10 11 /* DISPCC clock registers */ 12 #define DISPCC_PLL0 13 #define DISPCC_MDSS_AHB_CLK 14 #define DISPCC_MDSS_AHB_CLK_SRC 15 #define DISPCC_MDSS_BYTE0_CLK 16 #define DISPCC_MDSS_BYTE0_CLK_SRC 17 #define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 18 #define DISPCC_MDSS_BYTE0_INTF_CLK 19 #define DISPCC_MDSS_BYTE1_CLK 20 #define DISPCC_MDSS_BYTE1_CLK_SRC 21 #define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 22 #define DISPCC_MDSS_BYTE1_INTF_CLK 23 #define DISPCC_MDSS_DP_AUX_CLK 24 #define DISPCC_MDSS_DP_AUX_CLK_SRC 25 #define DISPCC_MDSS_DP_CRYPTO_CLK 26 #define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 27 #define DISPCC_MDSS_DP_LINK_CLK 28 #define DISPCC_MDSS_DP_LINK_CLK_SRC 29 #define DISPCC_MDSS_DP_LINK_INTF_CLK 30 #define DISPCC_MDSS_DP_PIXEL1_CLK 31 #define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 32 #define DISPCC_MDSS_DP_PIXEL_CLK 33 #define DISPCC_MDSS_DP_PIXEL_CLK_SRC 34 #define DISPCC_MDSS_ESC0_CLK 35 #define DISPCC_MDSS_ESC0_CLK_SRC 36 #define DISPCC_MDSS_ESC1_CLK 37 #define DISPCC_MDSS_ESC1_CLK_SRC 38 #define DISPCC_MDSS_MDP_CLK 39 #define DISPCC_MDSS_MDP_CLK_SRC 40 #define DISPCC_MDSS_MDP_LUT_CLK 41 #define DISPCC_MDSS_NON_GDSC_AHB_CLK 42 #define DISPCC_MDSS_PCLK0_CLK 43 #define DISPCC_MDSS_PCLK0_CLK_SRC 44 #define DISPCC_MDSS_PCLK1_CLK 45 #define DISPCC_MDSS_PCLK1_CLK_SRC 46 #define DISPCC_MDSS_ROT_CLK 47 #define DISPCC_MDSS_ROT_CLK_SRC 48 #define DISPCC_MDSS_RSCC_AHB_CLK 49 #define DISPCC_MDSS_RSCC_VSYNC_CLK 50 #define DISPCC_MDSS_VSYNC_CLK 51 #define DISPCC_MDSS_VSYNC_CLK_SRC 52 #define DISPCC_XO_CLK_SRC 53 #define DISPCC_SLEEP_CLK 54 #define DISPCC_SLEEP_CLK_SRC 55 56 /* DISPCC GDSCR */ 57 #define MDSS_GDSC 58 59 #endif 60
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