1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2022, The Linux Foundation. A 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H 8 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H 9 10 /* GCC clocks */ 11 #define GCC_AGGRE_NOC_PCIE_AXI_CLK 12 #define GCC_AGGRE_UFS_PHY_AXI_CLK 13 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 14 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 15 #define GCC_AHB2PHY_0_CLK 16 #define GCC_BOOT_ROM_AHB_CLK 17 #define GCC_CAMERA_AHB_CLK 18 #define GCC_CAMERA_HF_AXI_CLK 19 #define GCC_CAMERA_SF_AXI_CLK 20 #define GCC_CAMERA_XO_CLK 21 #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 22 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 #define GCC_CNOC_PCIE_SF_AXI_CLK 24 #define GCC_DDRSS_GPU_AXI_CLK 25 #define GCC_DDRSS_PCIE_SF_QTB_CLK 26 #define GCC_DISP_AHB_CLK 27 #define GCC_DISP_HF_AXI_CLK 28 #define GCC_DISP_XO_CLK 29 #define GCC_GP1_CLK 30 #define GCC_GP1_CLK_SRC 31 #define GCC_GP2_CLK 32 #define GCC_GP2_CLK_SRC 33 #define GCC_GP3_CLK 34 #define GCC_GP3_CLK_SRC 35 #define GCC_GPLL0 36 #define GCC_GPLL0_OUT_EVEN 37 #define GCC_GPLL4 38 #define GCC_GPLL7 39 #define GCC_GPLL9 40 #define GCC_GPU_CFG_AHB_CLK 41 #define GCC_GPU_GPLL0_CLK_SRC 42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 43 #define GCC_GPU_MEMNOC_GFX_CLK 44 #define GCC_GPU_SNOC_DVM_GFX_CLK 45 #define GCC_PCIE_0_AUX_CLK 46 #define GCC_PCIE_0_AUX_CLK_SRC 47 #define GCC_PCIE_0_CFG_AHB_CLK 48 #define GCC_PCIE_0_MSTR_AXI_CLK 49 #define GCC_PCIE_0_PHY_RCHNG_CLK 50 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 #define GCC_PCIE_0_PIPE_CLK 52 #define GCC_PCIE_0_PIPE_CLK_SRC 53 #define GCC_PCIE_0_SLV_AXI_CLK 54 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 #define GCC_PCIE_1_AUX_CLK 56 #define GCC_PCIE_1_AUX_CLK_SRC 57 #define GCC_PCIE_1_CFG_AHB_CLK 58 #define GCC_PCIE_1_MSTR_AXI_CLK 59 #define GCC_PCIE_1_PHY_AUX_CLK 60 #define GCC_PCIE_1_PHY_AUX_CLK_SRC 61 #define GCC_PCIE_1_PHY_RCHNG_CLK 62 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 #define GCC_PCIE_1_PIPE_CLK 64 #define GCC_PCIE_1_PIPE_CLK_SRC 65 #define GCC_PCIE_1_SLV_AXI_CLK 66 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 67 #define GCC_PDM2_CLK 68 #define GCC_PDM2_CLK_SRC 69 #define GCC_PDM_AHB_CLK 70 #define GCC_PDM_XO4_CLK 71 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 72 #define GCC_QMIP_CAMERA_RT_AHB_CLK 73 #define GCC_QMIP_DISP_AHB_CLK 74 #define GCC_QMIP_GPU_AHB_CLK 75 #define GCC_QMIP_PCIE_AHB_CLK 76 #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 77 #define GCC_QMIP_VIDEO_CVP_AHB_CLK 78 #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 79 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 80 #define GCC_QUPV3_I2C_CORE_CLK 81 #define GCC_QUPV3_I2C_S0_CLK 82 #define GCC_QUPV3_I2C_S0_CLK_SRC 83 #define GCC_QUPV3_I2C_S1_CLK 84 #define GCC_QUPV3_I2C_S1_CLK_SRC 85 #define GCC_QUPV3_I2C_S2_CLK 86 #define GCC_QUPV3_I2C_S2_CLK_SRC 87 #define GCC_QUPV3_I2C_S3_CLK 88 #define GCC_QUPV3_I2C_S3_CLK_SRC 89 #define GCC_QUPV3_I2C_S4_CLK 90 #define GCC_QUPV3_I2C_S4_CLK_SRC 91 #define GCC_QUPV3_I2C_S5_CLK 92 #define GCC_QUPV3_I2C_S5_CLK_SRC 93 #define GCC_QUPV3_I2C_S6_CLK 94 #define GCC_QUPV3_I2C_S6_CLK_SRC 95 #define GCC_QUPV3_I2C_S7_CLK 96 #define GCC_QUPV3_I2C_S7_CLK_SRC 97 #define GCC_QUPV3_I2C_S8_CLK 98 #define GCC_QUPV3_I2C_S8_CLK_SRC 99 #define GCC_QUPV3_I2C_S9_CLK 100 #define GCC_QUPV3_I2C_S9_CLK_SRC 101 #define GCC_QUPV3_I2C_S_AHB_CLK 102 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 103 #define GCC_QUPV3_WRAP1_CORE_CLK 104 #define GCC_QUPV3_WRAP1_S0_CLK 105 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 106 #define GCC_QUPV3_WRAP1_S1_CLK 107 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 108 #define GCC_QUPV3_WRAP1_S2_CLK 109 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 110 #define GCC_QUPV3_WRAP1_S3_CLK 111 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 112 #define GCC_QUPV3_WRAP1_S4_CLK 113 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 114 #define GCC_QUPV3_WRAP1_S5_CLK 115 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 116 #define GCC_QUPV3_WRAP1_S6_CLK 117 #define GCC_QUPV3_WRAP1_S6_CLK_SRC 118 #define GCC_QUPV3_WRAP1_S7_CLK 119 #define GCC_QUPV3_WRAP1_S7_CLK_SRC 120 #define GCC_QUPV3_WRAP2_CORE_2X_CLK 121 #define GCC_QUPV3_WRAP2_CORE_CLK 122 #define GCC_QUPV3_WRAP2_S0_CLK 123 #define GCC_QUPV3_WRAP2_S0_CLK_SRC 124 #define GCC_QUPV3_WRAP2_S1_CLK 125 #define GCC_QUPV3_WRAP2_S1_CLK_SRC 126 #define GCC_QUPV3_WRAP2_S2_CLK 127 #define GCC_QUPV3_WRAP2_S2_CLK_SRC 128 #define GCC_QUPV3_WRAP2_S3_CLK 129 #define GCC_QUPV3_WRAP2_S3_CLK_SRC 130 #define GCC_QUPV3_WRAP2_S4_CLK 131 #define GCC_QUPV3_WRAP2_S4_CLK_SRC 132 #define GCC_QUPV3_WRAP2_S5_CLK 133 #define GCC_QUPV3_WRAP2_S5_CLK_SRC 134 #define GCC_QUPV3_WRAP2_S6_CLK 135 #define GCC_QUPV3_WRAP2_S6_CLK_SRC 136 #define GCC_QUPV3_WRAP2_S7_CLK 137 #define GCC_QUPV3_WRAP2_S7_CLK_SRC 138 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 139 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 140 #define GCC_QUPV3_WRAP_2_M_AHB_CLK 141 #define GCC_QUPV3_WRAP_2_S_AHB_CLK 142 #define GCC_SDCC2_AHB_CLK 143 #define GCC_SDCC2_APPS_CLK 144 #define GCC_SDCC2_APPS_CLK_SRC 145 #define GCC_SDCC4_AHB_CLK 146 #define GCC_SDCC4_APPS_CLK 147 #define GCC_SDCC4_APPS_CLK_SRC 148 #define GCC_UFS_PHY_AHB_CLK 149 #define GCC_UFS_PHY_AXI_CLK 150 #define GCC_UFS_PHY_AXI_CLK_SRC 151 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 152 #define GCC_UFS_PHY_ICE_CORE_CLK 153 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 154 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 155 #define GCC_UFS_PHY_PHY_AUX_CLK 156 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 157 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 158 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 159 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 160 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 161 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 162 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 163 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 164 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 165 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 166 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 167 #define GCC_USB30_PRIM_MASTER_CLK 168 #define GCC_USB30_PRIM_MASTER_CLK_SRC 169 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 170 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_S 172 #define GCC_USB30_PRIM_SLEEP_CLK 173 #define GCC_USB3_PRIM_PHY_AUX_CLK 174 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176 #define GCC_USB3_PRIM_PHY_PIPE_CLK 177 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 178 #define GCC_VIDEO_AHB_CLK 179 #define GCC_VIDEO_AXI0_CLK 180 #define GCC_VIDEO_AXI1_CLK 181 #define GCC_VIDEO_XO_CLK 182 183 /* GCC resets */ 184 #define GCC_CAMERA_BCR 185 #define GCC_DISPLAY_BCR 186 #define GCC_GPU_BCR 187 #define GCC_PCIE_0_BCR 188 #define GCC_PCIE_0_LINK_DOWN_BCR 189 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 190 #define GCC_PCIE_0_PHY_BCR 191 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 192 #define GCC_PCIE_1_BCR 193 #define GCC_PCIE_1_LINK_DOWN_BCR 194 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 195 #define GCC_PCIE_1_PHY_BCR 196 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 197 #define GCC_PCIE_PHY_BCR 198 #define GCC_PCIE_PHY_CFG_AHB_BCR 199 #define GCC_PCIE_PHY_COM_BCR 200 #define GCC_PDM_BCR 201 #define GCC_QUPV3_WRAPPER_1_BCR 202 #define GCC_QUPV3_WRAPPER_2_BCR 203 #define GCC_QUPV3_WRAPPER_I2C_BCR 204 #define GCC_QUSB2PHY_PRIM_BCR 205 #define GCC_QUSB2PHY_SEC_BCR 206 #define GCC_SDCC2_BCR 207 #define GCC_SDCC4_BCR 208 #define GCC_UFS_PHY_BCR 209 #define GCC_USB30_PRIM_BCR 210 #define GCC_USB3_DP_PHY_PRIM_BCR 211 #define GCC_USB3_DP_PHY_SEC_BCR 212 #define GCC_USB3_PHY_PRIM_BCR 213 #define GCC_USB3_PHY_SEC_BCR 214 #define GCC_USB3PHY_PHY_PRIM_BCR 215 #define GCC_USB3PHY_PHY_SEC_BCR 216 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 217 #define GCC_VIDEO_AXI0_CLK_ARES 218 #define GCC_VIDEO_AXI1_CLK_ARES 219 #define GCC_VIDEO_BCR 220 221 /* GCC power domains */ 222 #define PCIE_0_GDSC 223 #define PCIE_0_PHY_GDSC 224 #define PCIE_1_GDSC 225 #define PCIE_1_PHY_GDSC 226 #define UFS_PHY_GDSC 227 #define UFS_MEM_PHY_GDSC 228 #define USB30_PRIM_GDSC 229 #define USB3_PHY_GDSC 230 231 #endif 232
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