1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Cen 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC 7 #define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC 8 9 /* DISP_CC clocks */ 10 #define DISP_CC_MDSS_ACCU_CLK 11 #define DISP_CC_MDSS_AHB1_CLK 12 #define DISP_CC_MDSS_AHB_CLK 13 #define DISP_CC_MDSS_AHB_CLK_SRC 14 #define DISP_CC_MDSS_BYTE0_CLK 15 #define DISP_CC_MDSS_BYTE0_CLK_SRC 16 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 17 #define DISP_CC_MDSS_BYTE0_INTF_CLK 18 #define DISP_CC_MDSS_BYTE1_CLK 19 #define DISP_CC_MDSS_BYTE1_CLK_SRC 20 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 21 #define DISP_CC_MDSS_BYTE1_INTF_CLK 22 #define DISP_CC_MDSS_DPTX0_AUX_CLK 23 #define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 24 #define DISP_CC_MDSS_DPTX0_LINK_CLK 25 #define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 26 #define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 27 #define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 28 #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 29 #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 30 #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 31 #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 32 #define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INT 33 #define DISP_CC_MDSS_DPTX1_AUX_CLK 34 #define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 35 #define DISP_CC_MDSS_DPTX1_LINK_CLK 36 #define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 37 #define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 38 #define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 39 #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 40 #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 41 #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 42 #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 43 #define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INT 44 #define DISP_CC_MDSS_DPTX2_AUX_CLK 45 #define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46 #define DISP_CC_MDSS_DPTX2_LINK_CLK 47 #define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 48 #define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 49 #define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 50 #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 51 #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 52 #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 53 #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 54 #define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INT 55 #define DISP_CC_MDSS_DPTX3_AUX_CLK 56 #define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57 #define DISP_CC_MDSS_DPTX3_LINK_CLK 58 #define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 59 #define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 60 #define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 61 #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 62 #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 63 #define DISP_CC_MDSS_ESC0_CLK 64 #define DISP_CC_MDSS_ESC0_CLK_SRC 65 #define DISP_CC_MDSS_ESC1_CLK 66 #define DISP_CC_MDSS_ESC1_CLK_SRC 67 #define DISP_CC_MDSS_MDP1_CLK 68 #define DISP_CC_MDSS_MDP_CLK 69 #define DISP_CC_MDSS_MDP_CLK_SRC 70 #define DISP_CC_MDSS_MDP_LUT1_CLK 71 #define DISP_CC_MDSS_MDP_LUT_CLK 72 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 73 #define DISP_CC_MDSS_PCLK0_CLK 74 #define DISP_CC_MDSS_PCLK0_CLK_SRC 75 #define DISP_CC_MDSS_PCLK1_CLK 76 #define DISP_CC_MDSS_PCLK1_CLK_SRC 77 #define DISP_CC_MDSS_RSCC_AHB_CLK 78 #define DISP_CC_MDSS_RSCC_VSYNC_CLK 79 #define DISP_CC_MDSS_VSYNC1_CLK 80 #define DISP_CC_MDSS_VSYNC_CLK 81 #define DISP_CC_MDSS_VSYNC_CLK_SRC 82 #define DISP_CC_PLL0 83 #define DISP_CC_PLL1 84 #define DISP_CC_SLEEP_CLK 85 #define DISP_CC_SLEEP_CLK_SRC 86 #define DISP_CC_XO_CLK 87 #define DISP_CC_XO_CLK_SRC 88 89 /* DISP_CC resets */ 90 #define DISP_CC_MDSS_CORE_BCR 91 #define DISP_CC_MDSS_CORE_INT2_BCR 92 #define DISP_CC_MDSS_RSCC_BCR 93 94 /* DISP_CC GDSCR */ 95 #define MDSS_GDSC 96 #define MDSS_INT2_GDSC 97 98 #endif 99
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