1 /* SPDX-License-Identifier: GPL-2.0+ !! 1 /*
2 * <<
3 * Copyright (C) 2016 Cogent Embedded Inc. 2 * Copyright (C) 2016 Cogent Embedded Inc.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License as published by
>> 6 * the Free Software Foundation; either version 2 of the License, or
>> 7 * (at your option) any later version.
4 */ 8 */
5 #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H 9 #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
6 #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H 10 #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
7 11
8 #include <dt-bindings/clock/renesas-cpg-mssr.h 12 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 13
10 /* r8a7743 CPG Core Clocks */ 14 /* r8a7743 CPG Core Clocks */
11 #define R8A7743_CLK_Z 0 15 #define R8A7743_CLK_Z 0
12 #define R8A7743_CLK_ZG 1 16 #define R8A7743_CLK_ZG 1
13 #define R8A7743_CLK_ZTR 2 17 #define R8A7743_CLK_ZTR 2
14 #define R8A7743_CLK_ZTRD2 3 18 #define R8A7743_CLK_ZTRD2 3
15 #define R8A7743_CLK_ZT 4 19 #define R8A7743_CLK_ZT 4
16 #define R8A7743_CLK_ZX 5 20 #define R8A7743_CLK_ZX 5
17 #define R8A7743_CLK_ZS 6 21 #define R8A7743_CLK_ZS 6
18 #define R8A7743_CLK_HP 7 22 #define R8A7743_CLK_HP 7
19 #define R8A7743_CLK_B 9 23 #define R8A7743_CLK_B 9
20 #define R8A7743_CLK_LB 10 24 #define R8A7743_CLK_LB 10
21 #define R8A7743_CLK_P 11 25 #define R8A7743_CLK_P 11
22 #define R8A7743_CLK_CL 12 26 #define R8A7743_CLK_CL 12
23 #define R8A7743_CLK_M2 13 27 #define R8A7743_CLK_M2 13
24 #define R8A7743_CLK_ZB3 15 28 #define R8A7743_CLK_ZB3 15
25 #define R8A7743_CLK_ZB3D2 16 29 #define R8A7743_CLK_ZB3D2 16
26 #define R8A7743_CLK_DDR 17 30 #define R8A7743_CLK_DDR 17
27 #define R8A7743_CLK_SDH 18 31 #define R8A7743_CLK_SDH 18
28 #define R8A7743_CLK_SD0 19 32 #define R8A7743_CLK_SD0 19
29 #define R8A7743_CLK_SD2 20 33 #define R8A7743_CLK_SD2 20
30 #define R8A7743_CLK_SD3 21 34 #define R8A7743_CLK_SD3 21
31 #define R8A7743_CLK_MMC0 22 35 #define R8A7743_CLK_MMC0 22
32 #define R8A7743_CLK_MP 23 36 #define R8A7743_CLK_MP 23
33 #define R8A7743_CLK_QSPI 26 37 #define R8A7743_CLK_QSPI 26
34 #define R8A7743_CLK_CP 27 38 #define R8A7743_CLK_CP 27
35 #define R8A7743_CLK_RCAN 28 39 #define R8A7743_CLK_RCAN 28
36 #define R8A7743_CLK_R 29 40 #define R8A7743_CLK_R 29
37 #define R8A7743_CLK_OSC 30 41 #define R8A7743_CLK_OSC 30
38 42
39 #endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR 43 #endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */
40 44
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