1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 2 /* 3 * Copyright (C) 2014 Ulrich Hecht 3 * Copyright (C) 2014 Ulrich Hecht 4 */ 4 */ 5 5 6 #ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ 6 #ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ 7 #define __DT_BINDINGS_CLOCK_R8A7778_H__ 7 #define __DT_BINDINGS_CLOCK_R8A7778_H__ 8 8 9 /* CPG */ 9 /* CPG */ 10 #define R8A7778_CLK_PLLA 0 10 #define R8A7778_CLK_PLLA 0 11 #define R8A7778_CLK_PLLB 1 11 #define R8A7778_CLK_PLLB 1 12 #define R8A7778_CLK_B 2 12 #define R8A7778_CLK_B 2 13 #define R8A7778_CLK_OUT 3 13 #define R8A7778_CLK_OUT 3 14 #define R8A7778_CLK_P 4 14 #define R8A7778_CLK_P 4 15 #define R8A7778_CLK_S 5 15 #define R8A7778_CLK_S 5 16 #define R8A7778_CLK_S1 6 16 #define R8A7778_CLK_S1 6 17 17 18 /* MSTP0 */ 18 /* MSTP0 */ 19 #define R8A7778_CLK_I2C0 30 19 #define R8A7778_CLK_I2C0 30 20 #define R8A7778_CLK_I2C1 29 20 #define R8A7778_CLK_I2C1 29 21 #define R8A7778_CLK_I2C2 28 21 #define R8A7778_CLK_I2C2 28 22 #define R8A7778_CLK_I2C3 27 22 #define R8A7778_CLK_I2C3 27 23 #define R8A7778_CLK_SCIF0 26 23 #define R8A7778_CLK_SCIF0 26 24 #define R8A7778_CLK_SCIF1 25 24 #define R8A7778_CLK_SCIF1 25 25 #define R8A7778_CLK_SCIF2 24 25 #define R8A7778_CLK_SCIF2 24 26 #define R8A7778_CLK_SCIF3 23 26 #define R8A7778_CLK_SCIF3 23 27 #define R8A7778_CLK_SCIF4 22 27 #define R8A7778_CLK_SCIF4 22 28 #define R8A7778_CLK_SCIF5 21 28 #define R8A7778_CLK_SCIF5 21 29 #define R8A7778_CLK_HSCIF0 19 29 #define R8A7778_CLK_HSCIF0 19 30 #define R8A7778_CLK_HSCIF1 18 30 #define R8A7778_CLK_HSCIF1 18 31 #define R8A7778_CLK_TMU0 16 31 #define R8A7778_CLK_TMU0 16 32 #define R8A7778_CLK_TMU1 15 32 #define R8A7778_CLK_TMU1 15 33 #define R8A7778_CLK_TMU2 14 33 #define R8A7778_CLK_TMU2 14 34 #define R8A7778_CLK_SSI0 12 34 #define R8A7778_CLK_SSI0 12 35 #define R8A7778_CLK_SSI1 11 35 #define R8A7778_CLK_SSI1 11 36 #define R8A7778_CLK_SSI2 10 36 #define R8A7778_CLK_SSI2 10 37 #define R8A7778_CLK_SSI3 9 37 #define R8A7778_CLK_SSI3 9 38 #define R8A7778_CLK_SRU 8 38 #define R8A7778_CLK_SRU 8 39 #define R8A7778_CLK_HSPI 7 39 #define R8A7778_CLK_HSPI 7 40 40 41 /* MSTP1 */ 41 /* MSTP1 */ 42 #define R8A7778_CLK_ETHER 14 42 #define R8A7778_CLK_ETHER 14 43 #define R8A7778_CLK_VIN0 10 43 #define R8A7778_CLK_VIN0 10 44 #define R8A7778_CLK_VIN1 9 44 #define R8A7778_CLK_VIN1 9 45 #define R8A7778_CLK_USB 0 45 #define R8A7778_CLK_USB 0 46 46 47 /* MSTP3 */ 47 /* MSTP3 */ 48 #define R8A7778_CLK_MMC 31 48 #define R8A7778_CLK_MMC 31 49 #define R8A7778_CLK_SDHI0 23 49 #define R8A7778_CLK_SDHI0 23 50 #define R8A7778_CLK_SDHI1 22 50 #define R8A7778_CLK_SDHI1 22 51 #define R8A7778_CLK_SDHI2 21 51 #define R8A7778_CLK_SDHI2 21 52 #define R8A7778_CLK_SSI4 11 52 #define R8A7778_CLK_SSI4 11 53 #define R8A7778_CLK_SSI5 10 53 #define R8A7778_CLK_SSI5 10 54 #define R8A7778_CLK_SSI6 9 54 #define R8A7778_CLK_SSI6 9 55 #define R8A7778_CLK_SSI7 8 55 #define R8A7778_CLK_SSI7 8 56 #define R8A7778_CLK_SSI8 7 56 #define R8A7778_CLK_SSI8 7 57 57 58 /* MSTP5 */ 58 /* MSTP5 */ 59 #define R8A7778_CLK_SRU_SRC0 31 59 #define R8A7778_CLK_SRU_SRC0 31 60 #define R8A7778_CLK_SRU_SRC1 30 60 #define R8A7778_CLK_SRU_SRC1 30 61 #define R8A7778_CLK_SRU_SRC2 29 61 #define R8A7778_CLK_SRU_SRC2 29 62 #define R8A7778_CLK_SRU_SRC3 28 62 #define R8A7778_CLK_SRU_SRC3 28 63 #define R8A7778_CLK_SRU_SRC4 27 63 #define R8A7778_CLK_SRU_SRC4 27 64 #define R8A7778_CLK_SRU_SRC5 26 64 #define R8A7778_CLK_SRU_SRC5 26 65 #define R8A7778_CLK_SRU_SRC6 25 65 #define R8A7778_CLK_SRU_SRC6 25 66 #define R8A7778_CLK_SRU_SRC7 24 66 #define R8A7778_CLK_SRU_SRC7 24 67 #define R8A7778_CLK_SRU_SRC8 23 67 #define R8A7778_CLK_SRU_SRC8 23 68 68 69 #endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ 69 #endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ 70 70
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