1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Copyright (c) 2015 Rockchip Electronics Co. 3 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
4 * Author: Xing Zheng <zhengxing@rock-chips.co 4 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 */ 5 */
6 6
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
9 9
10 /* core clocks */ 10 /* core clocks */
11 #define PLL_APLL 1 11 #define PLL_APLL 1
12 #define PLL_DPLL 2 12 #define PLL_DPLL 2
13 #define PLL_GPLL 3 13 #define PLL_GPLL 3
14 #define ARMCLK 4 14 #define ARMCLK 4
15 15
16 /* sclk gates (special clocks) */ 16 /* sclk gates (special clocks) */
17 #define SCLK_GPU 64 17 #define SCLK_GPU 64
18 #define SCLK_SPI 65 18 #define SCLK_SPI 65
19 #define SCLK_SDMMC 68 19 #define SCLK_SDMMC 68
20 #define SCLK_SDIO 69 20 #define SCLK_SDIO 69
21 #define SCLK_EMMC 71 21 #define SCLK_EMMC 71
22 #define SCLK_NANDC 76 22 #define SCLK_NANDC 76
23 #define SCLK_UART0 77 23 #define SCLK_UART0 77
24 #define SCLK_UART1 78 24 #define SCLK_UART1 78
25 #define SCLK_UART2 79 25 #define SCLK_UART2 79
26 #define SCLK_I2S 82 26 #define SCLK_I2S 82
27 #define SCLK_SPDIF 83 27 #define SCLK_SPDIF 83
28 #define SCLK_TIMER0 85 28 #define SCLK_TIMER0 85
29 #define SCLK_TIMER1 86 29 #define SCLK_TIMER1 86
30 #define SCLK_TIMER2 87 30 #define SCLK_TIMER2 87
31 #define SCLK_TIMER3 88 31 #define SCLK_TIMER3 88
32 #define SCLK_OTGPHY0 93 32 #define SCLK_OTGPHY0 93
33 #define SCLK_LCDC 100 33 #define SCLK_LCDC 100
34 #define SCLK_HDMI 109 34 #define SCLK_HDMI 109
35 #define SCLK_HEVC 111 35 #define SCLK_HEVC 111
36 #define SCLK_I2S_OUT 113 36 #define SCLK_I2S_OUT 113
37 #define SCLK_SDMMC_DRV 114 37 #define SCLK_SDMMC_DRV 114
38 #define SCLK_SDIO_DRV 115 38 #define SCLK_SDIO_DRV 115
39 #define SCLK_EMMC_DRV 117 39 #define SCLK_EMMC_DRV 117
40 #define SCLK_SDMMC_SAMPLE 118 40 #define SCLK_SDMMC_SAMPLE 118
41 #define SCLK_SDIO_SAMPLE 119 41 #define SCLK_SDIO_SAMPLE 119
42 #define SCLK_EMMC_SAMPLE 121 42 #define SCLK_EMMC_SAMPLE 121
43 #define SCLK_PVTM_CORE 123 43 #define SCLK_PVTM_CORE 123
44 #define SCLK_PVTM_GPU 124 44 #define SCLK_PVTM_GPU 124
45 #define SCLK_PVTM_VIDEO 125 45 #define SCLK_PVTM_VIDEO 125
46 #define SCLK_MAC 151 46 #define SCLK_MAC 151
47 #define SCLK_MACREF 152 47 #define SCLK_MACREF 152
48 #define SCLK_MACPLL 153 48 #define SCLK_MACPLL 153
49 #define SCLK_SFC 160 49 #define SCLK_SFC 160
50 50
51 /* aclk gates */ 51 /* aclk gates */
52 #define ACLK_DMAC2 194 52 #define ACLK_DMAC2 194
53 #define ACLK_LCDC 197 53 #define ACLK_LCDC 197
54 #define ACLK_VIO 203 54 #define ACLK_VIO 203
55 #define ACLK_VCODEC 208 55 #define ACLK_VCODEC 208
56 #define ACLK_CPU 209 56 #define ACLK_CPU 209
57 #define ACLK_PERI 210 57 #define ACLK_PERI 210
58 58
59 /* pclk gates */ 59 /* pclk gates */
60 #define PCLK_GPIO0 320 60 #define PCLK_GPIO0 320
61 #define PCLK_GPIO1 321 61 #define PCLK_GPIO1 321
62 #define PCLK_GPIO2 322 62 #define PCLK_GPIO2 322
63 #define PCLK_GRF 329 63 #define PCLK_GRF 329
64 #define PCLK_I2C0 332 64 #define PCLK_I2C0 332
65 #define PCLK_I2C1 333 65 #define PCLK_I2C1 333
66 #define PCLK_I2C2 334 66 #define PCLK_I2C2 334
67 #define PCLK_SPI 338 67 #define PCLK_SPI 338
68 #define PCLK_UART0 341 68 #define PCLK_UART0 341
69 #define PCLK_UART1 342 69 #define PCLK_UART1 342
70 #define PCLK_UART2 343 70 #define PCLK_UART2 343
71 #define PCLK_PWM 350 71 #define PCLK_PWM 350
72 #define PCLK_TIMER 353 72 #define PCLK_TIMER 353
73 #define PCLK_HDMI 360 73 #define PCLK_HDMI 360
74 #define PCLK_CPU 362 74 #define PCLK_CPU 362
75 #define PCLK_PERI 363 75 #define PCLK_PERI 363
76 #define PCLK_DDRUPCTL 364 76 #define PCLK_DDRUPCTL 364
77 #define PCLK_WDT 368 77 #define PCLK_WDT 368
78 #define PCLK_ACODEC 369 78 #define PCLK_ACODEC 369
79 79
80 /* hclk gates */ 80 /* hclk gates */
81 #define HCLK_OTG0 449 81 #define HCLK_OTG0 449
82 #define HCLK_OTG1 450 82 #define HCLK_OTG1 450
83 #define HCLK_NANDC 453 83 #define HCLK_NANDC 453
84 #define HCLK_SFC 454 84 #define HCLK_SFC 454
85 #define HCLK_SDMMC 456 85 #define HCLK_SDMMC 456
86 #define HCLK_SDIO 457 86 #define HCLK_SDIO 457
87 #define HCLK_EMMC 459 87 #define HCLK_EMMC 459
88 #define HCLK_MAC 460 88 #define HCLK_MAC 460
89 #define HCLK_I2S 462 89 #define HCLK_I2S 462
90 #define HCLK_LCDC 465 90 #define HCLK_LCDC 465
91 #define HCLK_ROM 467 91 #define HCLK_ROM 467
92 #define HCLK_VIO_BUS 472 92 #define HCLK_VIO_BUS 472
93 #define HCLK_VCODEC 476 93 #define HCLK_VCODEC 476
94 #define HCLK_CPU 477 94 #define HCLK_CPU 477
95 #define HCLK_PERI 478 95 #define HCLK_PERI 478
96 96
>> 97 #define CLK_NR_CLKS (HCLK_PERI + 1)
>> 98
97 /* soft-reset indices */ 99 /* soft-reset indices */
98 #define SRST_CORE0 0 100 #define SRST_CORE0 0
99 #define SRST_CORE1 1 101 #define SRST_CORE1 1
100 #define SRST_CORE0_DBG 4 102 #define SRST_CORE0_DBG 4
101 #define SRST_CORE1_DBG 5 103 #define SRST_CORE1_DBG 5
102 #define SRST_CORE0_POR 8 104 #define SRST_CORE0_POR 8
103 #define SRST_CORE1_POR 9 105 #define SRST_CORE1_POR 9
104 #define SRST_L2C 12 106 #define SRST_L2C 12
105 #define SRST_TOPDBG 13 107 #define SRST_TOPDBG 13
106 #define SRST_STRC_SYS_A 14 108 #define SRST_STRC_SYS_A 14
107 #define SRST_PD_CORE_NIU 15 109 #define SRST_PD_CORE_NIU 15
108 110
109 #define SRST_TIMER2 16 111 #define SRST_TIMER2 16
110 #define SRST_CPUSYS_H 17 112 #define SRST_CPUSYS_H 17
111 #define SRST_AHB2APB_H 19 113 #define SRST_AHB2APB_H 19
112 #define SRST_TIMER3 20 114 #define SRST_TIMER3 20
113 #define SRST_INTMEM 21 115 #define SRST_INTMEM 21
114 #define SRST_ROM 22 116 #define SRST_ROM 22
115 #define SRST_PERI_NIU 23 117 #define SRST_PERI_NIU 23
116 #define SRST_I2S 24 118 #define SRST_I2S 24
117 #define SRST_DDR_PLL 25 119 #define SRST_DDR_PLL 25
118 #define SRST_GPU_DLL 26 120 #define SRST_GPU_DLL 26
119 #define SRST_TIMER0 27 121 #define SRST_TIMER0 27
120 #define SRST_TIMER1 28 122 #define SRST_TIMER1 28
121 #define SRST_CORE_DLL 29 123 #define SRST_CORE_DLL 29
122 #define SRST_EFUSE_P 30 124 #define SRST_EFUSE_P 30
123 #define SRST_ACODEC_P 31 125 #define SRST_ACODEC_P 31
124 126
125 #define SRST_GPIO0 32 127 #define SRST_GPIO0 32
126 #define SRST_GPIO1 33 128 #define SRST_GPIO1 33
127 #define SRST_GPIO2 34 129 #define SRST_GPIO2 34
128 #define SRST_UART0 39 130 #define SRST_UART0 39
129 #define SRST_UART1 40 131 #define SRST_UART1 40
130 #define SRST_UART2 41 132 #define SRST_UART2 41
131 #define SRST_I2C0 43 133 #define SRST_I2C0 43
132 #define SRST_I2C1 44 134 #define SRST_I2C1 44
133 #define SRST_I2C2 45 135 #define SRST_I2C2 45
134 #define SRST_SFC 47 136 #define SRST_SFC 47
135 137
136 #define SRST_PWM0 48 138 #define SRST_PWM0 48
137 #define SRST_DAP 51 139 #define SRST_DAP 51
138 #define SRST_DAP_SYS 52 140 #define SRST_DAP_SYS 52
139 #define SRST_GRF 55 141 #define SRST_GRF 55
140 #define SRST_PERIPHSYS_A 57 142 #define SRST_PERIPHSYS_A 57
141 #define SRST_PERIPHSYS_H 58 143 #define SRST_PERIPHSYS_H 58
142 #define SRST_PERIPHSYS_P 59 144 #define SRST_PERIPHSYS_P 59
143 #define SRST_CPU_PERI 61 145 #define SRST_CPU_PERI 61
144 #define SRST_EMEM_PERI 62 146 #define SRST_EMEM_PERI 62
145 #define SRST_USB_PERI 63 147 #define SRST_USB_PERI 63
146 148
147 #define SRST_DMA2 64 149 #define SRST_DMA2 64
148 #define SRST_MAC 66 150 #define SRST_MAC 66
149 #define SRST_NANDC 68 151 #define SRST_NANDC 68
150 #define SRST_USBOTG0 69 152 #define SRST_USBOTG0 69
151 #define SRST_OTGC0 71 153 #define SRST_OTGC0 71
152 #define SRST_USBOTG1 72 154 #define SRST_USBOTG1 72
153 #define SRST_OTGC1 74 155 #define SRST_OTGC1 74
154 #define SRST_DDRMSCH 79 156 #define SRST_DDRMSCH 79
155 157
156 #define SRST_MMC0 81 158 #define SRST_MMC0 81
157 #define SRST_SDIO 82 159 #define SRST_SDIO 82
158 #define SRST_EMMC 83 160 #define SRST_EMMC 83
159 #define SRST_SPI0 84 161 #define SRST_SPI0 84
160 #define SRST_WDT 86 162 #define SRST_WDT 86
161 #define SRST_DDRPHY 88 163 #define SRST_DDRPHY 88
162 #define SRST_DDRPHY_P 89 164 #define SRST_DDRPHY_P 89
163 #define SRST_DDRCTRL 90 165 #define SRST_DDRCTRL 90
164 #define SRST_DDRCTRL_P 91 166 #define SRST_DDRCTRL_P 91
165 167
166 #define SRST_HDMI_P 96 168 #define SRST_HDMI_P 96
167 #define SRST_VIO_BUS_H 99 169 #define SRST_VIO_BUS_H 99
168 #define SRST_UTMI0 103 170 #define SRST_UTMI0 103
169 #define SRST_UTMI1 104 171 #define SRST_UTMI1 104
170 #define SRST_USBPOR 105 172 #define SRST_USBPOR 105
171 173
172 #define SRST_VCODEC_A 112 174 #define SRST_VCODEC_A 112
173 #define SRST_VCODEC_H 113 175 #define SRST_VCODEC_H 113
174 #define SRST_VIO1_A 114 176 #define SRST_VIO1_A 114
175 #define SRST_HEVC 115 177 #define SRST_HEVC 115
176 #define SRST_VCODEC_NIU_A 116 178 #define SRST_VCODEC_NIU_A 116
177 #define SRST_LCDC1_A 117 179 #define SRST_LCDC1_A 117
178 #define SRST_LCDC1_H 118 180 #define SRST_LCDC1_H 118
179 #define SRST_LCDC1_D 119 181 #define SRST_LCDC1_D 119
180 #define SRST_GPU 120 182 #define SRST_GPU 120
181 #define SRST_GPU_NIU_A 122 183 #define SRST_GPU_NIU_A 122
182 184
183 #define SRST_DBG_P 131 185 #define SRST_DBG_P 131
184 186
185 #endif 187 #endif
186 188
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