1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Copyright (c) 2017 Rockchip Electronics Co. 3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4 * Author: Elaine <zhangqing@rock-chips.com> 4 * Author: Elaine <zhangqing@rock-chips.com>
5 */ 5 */
6 6
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
9 9
10 /* core clocks */ 10 /* core clocks */
11 #define PLL_APLL 1 11 #define PLL_APLL 1
12 #define PLL_DPLL 2 12 #define PLL_DPLL 2
13 #define PLL_CPLL 3 13 #define PLL_CPLL 3
14 #define PLL_GPLL 4 14 #define PLL_GPLL 4
15 #define ARMCLK 5 15 #define ARMCLK 5
16 #define PLL_GPLL_DIV2 6 16 #define PLL_GPLL_DIV2 6
17 #define PLL_GPLL_DIV3 7 17 #define PLL_GPLL_DIV3 7
18 18
19 /* sclk gates (special clocks) */ 19 /* sclk gates (special clocks) */
20 #define SCLK_SPI0 65 20 #define SCLK_SPI0 65
21 #define SCLK_NANDC 67 21 #define SCLK_NANDC 67
22 #define SCLK_SDMMC 68 22 #define SCLK_SDMMC 68
23 #define SCLK_SDIO 69 23 #define SCLK_SDIO 69
24 #define SCLK_EMMC 71 24 #define SCLK_EMMC 71
25 #define SCLK_UART0 77 25 #define SCLK_UART0 77
26 #define SCLK_UART1 78 26 #define SCLK_UART1 78
27 #define SCLK_UART2 79 27 #define SCLK_UART2 79
28 #define SCLK_I2S0 80 28 #define SCLK_I2S0 80
29 #define SCLK_I2S1 81 29 #define SCLK_I2S1 81
30 #define SCLK_SPDIF 83 30 #define SCLK_SPDIF 83
31 #define SCLK_TIMER0 85 31 #define SCLK_TIMER0 85
32 #define SCLK_TIMER1 86 32 #define SCLK_TIMER1 86
33 #define SCLK_TIMER2 87 33 #define SCLK_TIMER2 87
34 #define SCLK_TIMER3 88 34 #define SCLK_TIMER3 88
35 #define SCLK_TIMER4 89 35 #define SCLK_TIMER4 89
36 #define SCLK_TIMER5 90 36 #define SCLK_TIMER5 90
37 #define SCLK_SARADC 91 37 #define SCLK_SARADC 91
38 #define SCLK_I2S_OUT 113 38 #define SCLK_I2S_OUT 113
39 #define SCLK_SDMMC_DRV 114 39 #define SCLK_SDMMC_DRV 114
40 #define SCLK_SDIO_DRV 115 40 #define SCLK_SDIO_DRV 115
41 #define SCLK_EMMC_DRV 117 41 #define SCLK_EMMC_DRV 117
42 #define SCLK_SDMMC_SAMPLE 118 42 #define SCLK_SDMMC_SAMPLE 118
43 #define SCLK_SDIO_SAMPLE 119 43 #define SCLK_SDIO_SAMPLE 119
44 #define SCLK_EMMC_SAMPLE 121 44 #define SCLK_EMMC_SAMPLE 121
45 #define SCLK_VOP 122 45 #define SCLK_VOP 122
46 #define SCLK_MAC_SRC 124 46 #define SCLK_MAC_SRC 124
47 #define SCLK_MAC 126 47 #define SCLK_MAC 126
48 #define SCLK_MAC_REFOUT 127 48 #define SCLK_MAC_REFOUT 127
49 #define SCLK_MAC_REF 128 49 #define SCLK_MAC_REF 128
50 #define SCLK_MAC_RX 129 50 #define SCLK_MAC_RX 129
51 #define SCLK_MAC_TX 130 51 #define SCLK_MAC_TX 130
52 #define SCLK_HEVC_CORE 134 52 #define SCLK_HEVC_CORE 134
53 #define SCLK_RGA 135 53 #define SCLK_RGA 135
54 #define SCLK_CRYPTO 138 54 #define SCLK_CRYPTO 138
55 #define SCLK_TSP 139 55 #define SCLK_TSP 139
56 #define SCLK_OTGPHY0 142 56 #define SCLK_OTGPHY0 142
57 #define SCLK_OTGPHY1 143 57 #define SCLK_OTGPHY1 143
58 #define SCLK_DDRC 144 58 #define SCLK_DDRC 144
59 #define SCLK_PVTM_FUNC 145 59 #define SCLK_PVTM_FUNC 145
60 #define SCLK_PVTM_CORE 146 60 #define SCLK_PVTM_CORE 146
61 #define SCLK_PVTM_GPU 147 61 #define SCLK_PVTM_GPU 147
62 #define SCLK_MIPI_24M 148 62 #define SCLK_MIPI_24M 148
63 #define SCLK_PVTM 149 63 #define SCLK_PVTM 149
64 #define SCLK_CIF_SRC 150 64 #define SCLK_CIF_SRC 150
65 #define SCLK_CIF_OUT_SRC 151 65 #define SCLK_CIF_OUT_SRC 151
66 #define SCLK_CIF_OUT 152 66 #define SCLK_CIF_OUT 152
67 #define SCLK_SFC 153 67 #define SCLK_SFC 153
68 #define SCLK_USB480M 154 68 #define SCLK_USB480M 154
69 69
70 /* dclk gates */ 70 /* dclk gates */
71 #define DCLK_VOP 190 71 #define DCLK_VOP 190
72 #define DCLK_EBC 191 72 #define DCLK_EBC 191
73 73
74 /* aclk gates */ 74 /* aclk gates */
75 #define ACLK_VIO0 192 75 #define ACLK_VIO0 192
76 #define ACLK_VIO1 193 76 #define ACLK_VIO1 193
77 #define ACLK_DMAC 194 77 #define ACLK_DMAC 194
78 #define ACLK_CPU 195 78 #define ACLK_CPU 195
79 #define ACLK_VEPU 196 79 #define ACLK_VEPU 196
80 #define ACLK_VDPU 197 80 #define ACLK_VDPU 197
81 #define ACLK_CIF 198 81 #define ACLK_CIF 198
82 #define ACLK_IEP 199 82 #define ACLK_IEP 199
83 #define ACLK_LCDC0 204 83 #define ACLK_LCDC0 204
84 #define ACLK_RGA 205 84 #define ACLK_RGA 205
85 #define ACLK_PERI 210 85 #define ACLK_PERI 210
86 #define ACLK_VOP 211 86 #define ACLK_VOP 211
87 #define ACLK_GMAC 212 87 #define ACLK_GMAC 212
88 #define ACLK_GPU 213 88 #define ACLK_GPU 213
89 89
90 /* pclk gates */ 90 /* pclk gates */
91 #define PCLK_SARADC 318 91 #define PCLK_SARADC 318
92 #define PCLK_WDT 319 92 #define PCLK_WDT 319
93 #define PCLK_GPIO0 320 93 #define PCLK_GPIO0 320
94 #define PCLK_GPIO1 321 94 #define PCLK_GPIO1 321
95 #define PCLK_GPIO2 322 95 #define PCLK_GPIO2 322
96 #define PCLK_GPIO3 323 96 #define PCLK_GPIO3 323
97 #define PCLK_VIO_H2P 324 97 #define PCLK_VIO_H2P 324
98 #define PCLK_MIPI 325 98 #define PCLK_MIPI 325
99 #define PCLK_EFUSE 326 99 #define PCLK_EFUSE 326
100 #define PCLK_HDMI 327 100 #define PCLK_HDMI 327
101 #define PCLK_ACODEC 328 101 #define PCLK_ACODEC 328
102 #define PCLK_GRF 329 102 #define PCLK_GRF 329
103 #define PCLK_I2C0 332 103 #define PCLK_I2C0 332
104 #define PCLK_I2C1 333 104 #define PCLK_I2C1 333
105 #define PCLK_I2C2 334 105 #define PCLK_I2C2 334
106 #define PCLK_I2C3 335 106 #define PCLK_I2C3 335
107 #define PCLK_SPI0 338 107 #define PCLK_SPI0 338
108 #define PCLK_UART0 341 108 #define PCLK_UART0 341
109 #define PCLK_UART1 342 109 #define PCLK_UART1 342
110 #define PCLK_UART2 343 110 #define PCLK_UART2 343
111 #define PCLK_TSADC 344 111 #define PCLK_TSADC 344
112 #define PCLK_PWM 350 112 #define PCLK_PWM 350
113 #define PCLK_TIMER 353 113 #define PCLK_TIMER 353
114 #define PCLK_CPU 354 114 #define PCLK_CPU 354
115 #define PCLK_PERI 363 115 #define PCLK_PERI 363
116 #define PCLK_GMAC 367 116 #define PCLK_GMAC 367
117 #define PCLK_PMU_PRE 368 117 #define PCLK_PMU_PRE 368
118 #define PCLK_SIM_CARD 369 118 #define PCLK_SIM_CARD 369
119 #define PCLK_MIPIPHY 370 <<
120 119
121 /* hclk gates */ 120 /* hclk gates */
122 #define HCLK_SPDIF 440 121 #define HCLK_SPDIF 440
123 #define HCLK_GPS 441 122 #define HCLK_GPS 441
124 #define HCLK_USBHOST 442 123 #define HCLK_USBHOST 442
125 #define HCLK_I2S_8CH 443 124 #define HCLK_I2S_8CH 443
126 #define HCLK_I2S_2CH 444 125 #define HCLK_I2S_2CH 444
127 #define HCLK_VOP 452 126 #define HCLK_VOP 452
128 #define HCLK_NANDC 453 127 #define HCLK_NANDC 453
129 #define HCLK_SDMMC 456 128 #define HCLK_SDMMC 456
130 #define HCLK_SDIO 457 129 #define HCLK_SDIO 457
131 #define HCLK_EMMC 459 130 #define HCLK_EMMC 459
132 #define HCLK_CPU 460 131 #define HCLK_CPU 460
133 #define HCLK_VEPU 461 132 #define HCLK_VEPU 461
134 #define HCLK_VDPU 462 133 #define HCLK_VDPU 462
135 #define HCLK_LCDC0 463 134 #define HCLK_LCDC0 463
136 #define HCLK_EBC 465 135 #define HCLK_EBC 465
137 #define HCLK_VIO 466 136 #define HCLK_VIO 466
138 #define HCLK_RGA 467 137 #define HCLK_RGA 467
139 #define HCLK_IEP 468 138 #define HCLK_IEP 468
140 #define HCLK_VIO_H2P 469 139 #define HCLK_VIO_H2P 469
141 #define HCLK_CIF 470 140 #define HCLK_CIF 470
142 #define HCLK_HOST2 473 141 #define HCLK_HOST2 473
143 #define HCLK_OTG 474 142 #define HCLK_OTG 474
144 #define HCLK_TSP 475 143 #define HCLK_TSP 475
145 #define HCLK_CRYPTO 476 144 #define HCLK_CRYPTO 476
146 #define HCLK_PERI 478 145 #define HCLK_PERI 478
147 #define HCLK_SFC 479 !! 146
>> 147 #define CLK_NR_CLKS (HCLK_PERI + 1)
148 148
149 /* soft-reset indices */ 149 /* soft-reset indices */
150 #define SRST_CORE0_PO 0 150 #define SRST_CORE0_PO 0
151 #define SRST_CORE1_PO 1 151 #define SRST_CORE1_PO 1
152 #define SRST_CORE2_PO 2 152 #define SRST_CORE2_PO 2
153 #define SRST_CORE3_PO 3 153 #define SRST_CORE3_PO 3
154 #define SRST_CORE0 4 154 #define SRST_CORE0 4
155 #define SRST_CORE1 5 155 #define SRST_CORE1 5
156 #define SRST_CORE2 6 156 #define SRST_CORE2 6
157 #define SRST_CORE3 7 157 #define SRST_CORE3 7
158 #define SRST_CORE0_DBG 8 158 #define SRST_CORE0_DBG 8
159 #define SRST_CORE1_DBG 9 159 #define SRST_CORE1_DBG 9
160 #define SRST_CORE2_DBG 10 160 #define SRST_CORE2_DBG 10
161 #define SRST_CORE3_DBG 11 161 #define SRST_CORE3_DBG 11
162 #define SRST_TOPDBG 12 162 #define SRST_TOPDBG 12
163 #define SRST_ACLK_CORE 13 163 #define SRST_ACLK_CORE 13
164 #define SRST_STRC_SYS_A 14 164 #define SRST_STRC_SYS_A 14
165 #define SRST_L2C 15 165 #define SRST_L2C 15
166 166
167 #define SRST_CPUSYS_H 18 167 #define SRST_CPUSYS_H 18
168 #define SRST_AHB2APBSYS_H 19 168 #define SRST_AHB2APBSYS_H 19
169 #define SRST_SPDIF 20 169 #define SRST_SPDIF 20
170 #define SRST_INTMEM 21 170 #define SRST_INTMEM 21
171 #define SRST_ROM 22 171 #define SRST_ROM 22
172 #define SRST_PERI_NIU 23 172 #define SRST_PERI_NIU 23
173 #define SRST_I2S_2CH 24 173 #define SRST_I2S_2CH 24
174 #define SRST_I2S_8CH 25 174 #define SRST_I2S_8CH 25
175 #define SRST_GPU_PVTM 26 175 #define SRST_GPU_PVTM 26
176 #define SRST_FUNC_PVTM 27 176 #define SRST_FUNC_PVTM 27
177 #define SRST_CORE_PVTM 29 177 #define SRST_CORE_PVTM 29
178 #define SRST_EFUSE_P 30 178 #define SRST_EFUSE_P 30
179 #define SRST_ACODEC_P 31 179 #define SRST_ACODEC_P 31
180 180
181 #define SRST_GPIO0 32 181 #define SRST_GPIO0 32
182 #define SRST_GPIO1 33 182 #define SRST_GPIO1 33
183 #define SRST_GPIO2 34 183 #define SRST_GPIO2 34
184 #define SRST_GPIO3 35 184 #define SRST_GPIO3 35
185 #define SRST_MIPIPHY_P 36 185 #define SRST_MIPIPHY_P 36
186 #define SRST_UART0 39 186 #define SRST_UART0 39
187 #define SRST_UART1 40 187 #define SRST_UART1 40
188 #define SRST_UART2 41 188 #define SRST_UART2 41
189 #define SRST_I2C0 43 189 #define SRST_I2C0 43
190 #define SRST_I2C1 44 190 #define SRST_I2C1 44
191 #define SRST_I2C2 45 191 #define SRST_I2C2 45
192 #define SRST_I2C3 46 192 #define SRST_I2C3 46
193 #define SRST_SFC 47 193 #define SRST_SFC 47
194 194
195 #define SRST_PWM 48 195 #define SRST_PWM 48
196 #define SRST_DAP_PO 50 196 #define SRST_DAP_PO 50
197 #define SRST_DAP 51 197 #define SRST_DAP 51
198 #define SRST_DAP_SYS 52 198 #define SRST_DAP_SYS 52
199 #define SRST_CRYPTO 53 199 #define SRST_CRYPTO 53
200 #define SRST_GRF 55 200 #define SRST_GRF 55
201 #define SRST_GMAC 56 201 #define SRST_GMAC 56
202 #define SRST_PERIPH_SYS_A 57 202 #define SRST_PERIPH_SYS_A 57
203 #define SRST_PERIPH_SYS_H 58 203 #define SRST_PERIPH_SYS_H 58
204 #define SRST_PERIPH_SYS_P 59 204 #define SRST_PERIPH_SYS_P 59
205 #define SRST_SMART_CARD 60 205 #define SRST_SMART_CARD 60
206 #define SRST_CPU_PERI 61 206 #define SRST_CPU_PERI 61
207 #define SRST_EMEM_PERI 62 207 #define SRST_EMEM_PERI 62
208 #define SRST_USB_PERI 63 208 #define SRST_USB_PERI 63
209 209
210 #define SRST_DMA 64 210 #define SRST_DMA 64
211 #define SRST_GPS 67 211 #define SRST_GPS 67
212 #define SRST_NANDC 68 212 #define SRST_NANDC 68
213 #define SRST_USBOTG0 69 213 #define SRST_USBOTG0 69
214 #define SRST_OTGC0 71 214 #define SRST_OTGC0 71
215 #define SRST_USBOTG1 72 215 #define SRST_USBOTG1 72
216 #define SRST_OTGC1 74 216 #define SRST_OTGC1 74
217 #define SRST_DDRMSCH 79 217 #define SRST_DDRMSCH 79
218 218
219 #define SRST_SDMMC 81 219 #define SRST_SDMMC 81
220 #define SRST_SDIO 82 220 #define SRST_SDIO 82
221 #define SRST_EMMC 83 221 #define SRST_EMMC 83
222 #define SRST_SPI 84 222 #define SRST_SPI 84
223 #define SRST_WDT 86 223 #define SRST_WDT 86
224 #define SRST_SARADC 87 224 #define SRST_SARADC 87
225 #define SRST_DDRPHY 88 225 #define SRST_DDRPHY 88
226 #define SRST_DDRPHY_P 89 226 #define SRST_DDRPHY_P 89
227 #define SRST_DDRCTRL 90 227 #define SRST_DDRCTRL 90
228 #define SRST_DDRCTRL_P 91 228 #define SRST_DDRCTRL_P 91
229 #define SRST_TSP 92 229 #define SRST_TSP 92
230 #define SRST_TSP_CLKIN 93 230 #define SRST_TSP_CLKIN 93
231 #define SRST_HOST0_ECHI 94 231 #define SRST_HOST0_ECHI 94
232 232
233 #define SRST_HDMI_P 96 233 #define SRST_HDMI_P 96
234 #define SRST_VIO_ARBI_H 97 234 #define SRST_VIO_ARBI_H 97
235 #define SRST_VIO0_A 98 235 #define SRST_VIO0_A 98
236 #define SRST_VIO_BUS_H 99 236 #define SRST_VIO_BUS_H 99
237 #define SRST_VOP_A 100 237 #define SRST_VOP_A 100
238 #define SRST_VOP_H 101 238 #define SRST_VOP_H 101
239 #define SRST_VOP_D 102 239 #define SRST_VOP_D 102
240 #define SRST_UTMI0 103 240 #define SRST_UTMI0 103
241 #define SRST_UTMI1 104 241 #define SRST_UTMI1 104
242 #define SRST_USBPOR 105 242 #define SRST_USBPOR 105
243 #define SRST_IEP_A 106 243 #define SRST_IEP_A 106
244 #define SRST_IEP_H 107 244 #define SRST_IEP_H 107
245 #define SRST_RGA_A 108 245 #define SRST_RGA_A 108
246 #define SRST_RGA_H 109 246 #define SRST_RGA_H 109
247 #define SRST_CIF0 110 247 #define SRST_CIF0 110
248 #define SRST_PMU 111 248 #define SRST_PMU 111
249 249
250 #define SRST_VCODEC_A 112 250 #define SRST_VCODEC_A 112
251 #define SRST_VCODEC_H 113 251 #define SRST_VCODEC_H 113
252 #define SRST_VIO1_A 114 252 #define SRST_VIO1_A 114
253 #define SRST_HEVC_CORE 115 253 #define SRST_HEVC_CORE 115
254 #define SRST_VCODEC_NIU_A 116 254 #define SRST_VCODEC_NIU_A 116
255 #define SRST_PMU_NIU_P 117 255 #define SRST_PMU_NIU_P 117
256 #define SRST_LCDC0_S 119 256 #define SRST_LCDC0_S 119
257 #define SRST_GPU 120 257 #define SRST_GPU 120
258 #define SRST_GPU_NIU_A 122 258 #define SRST_GPU_NIU_A 122
259 #define SRST_EBC_A 123 259 #define SRST_EBC_A 123
260 #define SRST_EBC_H 124 260 #define SRST_EBC_H 124
261 261
262 #define SRST_CORE_DBG 128 262 #define SRST_CORE_DBG 128
263 #define SRST_DBG_P 129 263 #define SRST_DBG_P 129
264 #define SRST_TIMER0 130 264 #define SRST_TIMER0 130
265 #define SRST_TIMER1 131 265 #define SRST_TIMER1 131
266 #define SRST_TIMER2 132 266 #define SRST_TIMER2 132
267 #define SRST_TIMER3 133 267 #define SRST_TIMER3 133
268 #define SRST_TIMER4 134 268 #define SRST_TIMER4 134
269 #define SRST_TIMER5 135 269 #define SRST_TIMER5 135
270 #define SRST_VIO_H2P 136 270 #define SRST_VIO_H2P 136
271 #define SRST_VIO_MIPI_DSI 137 271 #define SRST_VIO_MIPI_DSI 137
272 272
273 #endif 273 #endif
274 274
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