1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2017 Rockchip Electronics Co. 2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4 * Author: Elaine <zhangqing@rock-chips.com> 3 * Author: Elaine <zhangqing@rock-chips.com>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
9 18
10 /* core clocks */ 19 /* core clocks */
11 #define PLL_APLL 1 20 #define PLL_APLL 1
12 #define PLL_DPLL 2 21 #define PLL_DPLL 2
13 #define PLL_CPLL 3 22 #define PLL_CPLL 3
14 #define PLL_GPLL 4 23 #define PLL_GPLL 4
15 #define ARMCLK 5 24 #define ARMCLK 5
16 #define PLL_GPLL_DIV2 6 25 #define PLL_GPLL_DIV2 6
17 #define PLL_GPLL_DIV3 7 26 #define PLL_GPLL_DIV3 7
18 27
19 /* sclk gates (special clocks) */ 28 /* sclk gates (special clocks) */
20 #define SCLK_SPI0 65 29 #define SCLK_SPI0 65
21 #define SCLK_NANDC 67 30 #define SCLK_NANDC 67
22 #define SCLK_SDMMC 68 31 #define SCLK_SDMMC 68
23 #define SCLK_SDIO 69 32 #define SCLK_SDIO 69
24 #define SCLK_EMMC 71 33 #define SCLK_EMMC 71
25 #define SCLK_UART0 77 34 #define SCLK_UART0 77
26 #define SCLK_UART1 78 35 #define SCLK_UART1 78
27 #define SCLK_UART2 79 36 #define SCLK_UART2 79
28 #define SCLK_I2S0 80 37 #define SCLK_I2S0 80
29 #define SCLK_I2S1 81 38 #define SCLK_I2S1 81
30 #define SCLK_SPDIF 83 39 #define SCLK_SPDIF 83
31 #define SCLK_TIMER0 85 40 #define SCLK_TIMER0 85
32 #define SCLK_TIMER1 86 41 #define SCLK_TIMER1 86
33 #define SCLK_TIMER2 87 42 #define SCLK_TIMER2 87
34 #define SCLK_TIMER3 88 43 #define SCLK_TIMER3 88
35 #define SCLK_TIMER4 89 44 #define SCLK_TIMER4 89
36 #define SCLK_TIMER5 90 45 #define SCLK_TIMER5 90
37 #define SCLK_SARADC 91 46 #define SCLK_SARADC 91
38 #define SCLK_I2S_OUT 113 47 #define SCLK_I2S_OUT 113
39 #define SCLK_SDMMC_DRV 114 48 #define SCLK_SDMMC_DRV 114
40 #define SCLK_SDIO_DRV 115 49 #define SCLK_SDIO_DRV 115
41 #define SCLK_EMMC_DRV 117 50 #define SCLK_EMMC_DRV 117
42 #define SCLK_SDMMC_SAMPLE 118 51 #define SCLK_SDMMC_SAMPLE 118
43 #define SCLK_SDIO_SAMPLE 119 52 #define SCLK_SDIO_SAMPLE 119
44 #define SCLK_EMMC_SAMPLE 121 53 #define SCLK_EMMC_SAMPLE 121
45 #define SCLK_VOP 122 54 #define SCLK_VOP 122
46 #define SCLK_MAC_SRC 124 55 #define SCLK_MAC_SRC 124
47 #define SCLK_MAC 126 56 #define SCLK_MAC 126
48 #define SCLK_MAC_REFOUT 127 57 #define SCLK_MAC_REFOUT 127
49 #define SCLK_MAC_REF 128 58 #define SCLK_MAC_REF 128
50 #define SCLK_MAC_RX 129 59 #define SCLK_MAC_RX 129
51 #define SCLK_MAC_TX 130 60 #define SCLK_MAC_TX 130
52 #define SCLK_HEVC_CORE 134 61 #define SCLK_HEVC_CORE 134
53 #define SCLK_RGA 135 62 #define SCLK_RGA 135
54 #define SCLK_CRYPTO 138 63 #define SCLK_CRYPTO 138
55 #define SCLK_TSP 139 64 #define SCLK_TSP 139
56 #define SCLK_OTGPHY0 142 65 #define SCLK_OTGPHY0 142
57 #define SCLK_OTGPHY1 143 66 #define SCLK_OTGPHY1 143
58 #define SCLK_DDRC 144 67 #define SCLK_DDRC 144
59 #define SCLK_PVTM_FUNC 145 68 #define SCLK_PVTM_FUNC 145
60 #define SCLK_PVTM_CORE 146 69 #define SCLK_PVTM_CORE 146
61 #define SCLK_PVTM_GPU 147 70 #define SCLK_PVTM_GPU 147
62 #define SCLK_MIPI_24M 148 71 #define SCLK_MIPI_24M 148
63 #define SCLK_PVTM 149 72 #define SCLK_PVTM 149
64 #define SCLK_CIF_SRC 150 73 #define SCLK_CIF_SRC 150
65 #define SCLK_CIF_OUT_SRC 151 74 #define SCLK_CIF_OUT_SRC 151
66 #define SCLK_CIF_OUT 152 75 #define SCLK_CIF_OUT 152
67 #define SCLK_SFC 153 76 #define SCLK_SFC 153
68 #define SCLK_USB480M 154 77 #define SCLK_USB480M 154
69 78
70 /* dclk gates */ 79 /* dclk gates */
71 #define DCLK_VOP 190 80 #define DCLK_VOP 190
72 #define DCLK_EBC 191 81 #define DCLK_EBC 191
73 82
74 /* aclk gates */ 83 /* aclk gates */
75 #define ACLK_VIO0 192 84 #define ACLK_VIO0 192
76 #define ACLK_VIO1 193 85 #define ACLK_VIO1 193
77 #define ACLK_DMAC 194 86 #define ACLK_DMAC 194
78 #define ACLK_CPU 195 87 #define ACLK_CPU 195
79 #define ACLK_VEPU 196 88 #define ACLK_VEPU 196
80 #define ACLK_VDPU 197 89 #define ACLK_VDPU 197
81 #define ACLK_CIF 198 90 #define ACLK_CIF 198
82 #define ACLK_IEP 199 91 #define ACLK_IEP 199
83 #define ACLK_LCDC0 204 92 #define ACLK_LCDC0 204
84 #define ACLK_RGA 205 93 #define ACLK_RGA 205
85 #define ACLK_PERI 210 94 #define ACLK_PERI 210
86 #define ACLK_VOP 211 95 #define ACLK_VOP 211
87 #define ACLK_GMAC 212 96 #define ACLK_GMAC 212
88 #define ACLK_GPU 213 97 #define ACLK_GPU 213
89 98
90 /* pclk gates */ 99 /* pclk gates */
91 #define PCLK_SARADC 318 100 #define PCLK_SARADC 318
92 #define PCLK_WDT 319 101 #define PCLK_WDT 319
93 #define PCLK_GPIO0 320 102 #define PCLK_GPIO0 320
94 #define PCLK_GPIO1 321 103 #define PCLK_GPIO1 321
95 #define PCLK_GPIO2 322 104 #define PCLK_GPIO2 322
96 #define PCLK_GPIO3 323 105 #define PCLK_GPIO3 323
97 #define PCLK_VIO_H2P 324 106 #define PCLK_VIO_H2P 324
98 #define PCLK_MIPI 325 107 #define PCLK_MIPI 325
99 #define PCLK_EFUSE 326 108 #define PCLK_EFUSE 326
100 #define PCLK_HDMI 327 109 #define PCLK_HDMI 327
101 #define PCLK_ACODEC 328 110 #define PCLK_ACODEC 328
102 #define PCLK_GRF 329 111 #define PCLK_GRF 329
103 #define PCLK_I2C0 332 112 #define PCLK_I2C0 332
104 #define PCLK_I2C1 333 113 #define PCLK_I2C1 333
105 #define PCLK_I2C2 334 114 #define PCLK_I2C2 334
106 #define PCLK_I2C3 335 115 #define PCLK_I2C3 335
107 #define PCLK_SPI0 338 116 #define PCLK_SPI0 338
108 #define PCLK_UART0 341 117 #define PCLK_UART0 341
109 #define PCLK_UART1 342 118 #define PCLK_UART1 342
110 #define PCLK_UART2 343 119 #define PCLK_UART2 343
111 #define PCLK_TSADC 344 120 #define PCLK_TSADC 344
112 #define PCLK_PWM 350 121 #define PCLK_PWM 350
113 #define PCLK_TIMER 353 122 #define PCLK_TIMER 353
114 #define PCLK_CPU 354 123 #define PCLK_CPU 354
115 #define PCLK_PERI 363 124 #define PCLK_PERI 363
116 #define PCLK_GMAC 367 125 #define PCLK_GMAC 367
117 #define PCLK_PMU_PRE 368 126 #define PCLK_PMU_PRE 368
118 #define PCLK_SIM_CARD 369 127 #define PCLK_SIM_CARD 369
119 #define PCLK_MIPIPHY 370 <<
120 128
121 /* hclk gates */ 129 /* hclk gates */
122 #define HCLK_SPDIF 440 130 #define HCLK_SPDIF 440
123 #define HCLK_GPS 441 131 #define HCLK_GPS 441
124 #define HCLK_USBHOST 442 132 #define HCLK_USBHOST 442
125 #define HCLK_I2S_8CH 443 133 #define HCLK_I2S_8CH 443
126 #define HCLK_I2S_2CH 444 134 #define HCLK_I2S_2CH 444
127 #define HCLK_VOP 452 135 #define HCLK_VOP 452
128 #define HCLK_NANDC 453 136 #define HCLK_NANDC 453
129 #define HCLK_SDMMC 456 137 #define HCLK_SDMMC 456
130 #define HCLK_SDIO 457 138 #define HCLK_SDIO 457
131 #define HCLK_EMMC 459 139 #define HCLK_EMMC 459
132 #define HCLK_CPU 460 140 #define HCLK_CPU 460
133 #define HCLK_VEPU 461 141 #define HCLK_VEPU 461
134 #define HCLK_VDPU 462 142 #define HCLK_VDPU 462
135 #define HCLK_LCDC0 463 143 #define HCLK_LCDC0 463
136 #define HCLK_EBC 465 144 #define HCLK_EBC 465
137 #define HCLK_VIO 466 145 #define HCLK_VIO 466
138 #define HCLK_RGA 467 146 #define HCLK_RGA 467
139 #define HCLK_IEP 468 147 #define HCLK_IEP 468
140 #define HCLK_VIO_H2P 469 148 #define HCLK_VIO_H2P 469
141 #define HCLK_CIF 470 149 #define HCLK_CIF 470
142 #define HCLK_HOST2 473 150 #define HCLK_HOST2 473
143 #define HCLK_OTG 474 151 #define HCLK_OTG 474
144 #define HCLK_TSP 475 152 #define HCLK_TSP 475
145 #define HCLK_CRYPTO 476 153 #define HCLK_CRYPTO 476
146 #define HCLK_PERI 478 154 #define HCLK_PERI 478
147 #define HCLK_SFC 479 !! 155
>> 156 #define CLK_NR_CLKS (HCLK_PERI + 1)
148 157
149 /* soft-reset indices */ 158 /* soft-reset indices */
150 #define SRST_CORE0_PO 0 159 #define SRST_CORE0_PO 0
151 #define SRST_CORE1_PO 1 160 #define SRST_CORE1_PO 1
152 #define SRST_CORE2_PO 2 161 #define SRST_CORE2_PO 2
153 #define SRST_CORE3_PO 3 162 #define SRST_CORE3_PO 3
154 #define SRST_CORE0 4 163 #define SRST_CORE0 4
155 #define SRST_CORE1 5 164 #define SRST_CORE1 5
156 #define SRST_CORE2 6 165 #define SRST_CORE2 6
157 #define SRST_CORE3 7 166 #define SRST_CORE3 7
158 #define SRST_CORE0_DBG 8 167 #define SRST_CORE0_DBG 8
159 #define SRST_CORE1_DBG 9 168 #define SRST_CORE1_DBG 9
160 #define SRST_CORE2_DBG 10 169 #define SRST_CORE2_DBG 10
161 #define SRST_CORE3_DBG 11 170 #define SRST_CORE3_DBG 11
162 #define SRST_TOPDBG 12 171 #define SRST_TOPDBG 12
163 #define SRST_ACLK_CORE 13 172 #define SRST_ACLK_CORE 13
164 #define SRST_STRC_SYS_A 14 173 #define SRST_STRC_SYS_A 14
165 #define SRST_L2C 15 174 #define SRST_L2C 15
166 175
167 #define SRST_CPUSYS_H 18 176 #define SRST_CPUSYS_H 18
168 #define SRST_AHB2APBSYS_H 19 177 #define SRST_AHB2APBSYS_H 19
169 #define SRST_SPDIF 20 178 #define SRST_SPDIF 20
170 #define SRST_INTMEM 21 179 #define SRST_INTMEM 21
171 #define SRST_ROM 22 180 #define SRST_ROM 22
172 #define SRST_PERI_NIU 23 181 #define SRST_PERI_NIU 23
173 #define SRST_I2S_2CH 24 182 #define SRST_I2S_2CH 24
174 #define SRST_I2S_8CH 25 183 #define SRST_I2S_8CH 25
175 #define SRST_GPU_PVTM 26 184 #define SRST_GPU_PVTM 26
176 #define SRST_FUNC_PVTM 27 185 #define SRST_FUNC_PVTM 27
177 #define SRST_CORE_PVTM 29 186 #define SRST_CORE_PVTM 29
178 #define SRST_EFUSE_P 30 187 #define SRST_EFUSE_P 30
179 #define SRST_ACODEC_P 31 188 #define SRST_ACODEC_P 31
180 189
181 #define SRST_GPIO0 32 190 #define SRST_GPIO0 32
182 #define SRST_GPIO1 33 191 #define SRST_GPIO1 33
183 #define SRST_GPIO2 34 192 #define SRST_GPIO2 34
184 #define SRST_GPIO3 35 193 #define SRST_GPIO3 35
185 #define SRST_MIPIPHY_P 36 194 #define SRST_MIPIPHY_P 36
186 #define SRST_UART0 39 195 #define SRST_UART0 39
187 #define SRST_UART1 40 196 #define SRST_UART1 40
188 #define SRST_UART2 41 197 #define SRST_UART2 41
189 #define SRST_I2C0 43 198 #define SRST_I2C0 43
190 #define SRST_I2C1 44 199 #define SRST_I2C1 44
191 #define SRST_I2C2 45 200 #define SRST_I2C2 45
192 #define SRST_I2C3 46 201 #define SRST_I2C3 46
193 #define SRST_SFC 47 202 #define SRST_SFC 47
194 203
195 #define SRST_PWM 48 204 #define SRST_PWM 48
196 #define SRST_DAP_PO 50 205 #define SRST_DAP_PO 50
197 #define SRST_DAP 51 206 #define SRST_DAP 51
198 #define SRST_DAP_SYS 52 207 #define SRST_DAP_SYS 52
199 #define SRST_CRYPTO 53 208 #define SRST_CRYPTO 53
200 #define SRST_GRF 55 209 #define SRST_GRF 55
201 #define SRST_GMAC 56 210 #define SRST_GMAC 56
202 #define SRST_PERIPH_SYS_A 57 211 #define SRST_PERIPH_SYS_A 57
203 #define SRST_PERIPH_SYS_H 58 212 #define SRST_PERIPH_SYS_H 58
204 #define SRST_PERIPH_SYS_P 59 213 #define SRST_PERIPH_SYS_P 59
205 #define SRST_SMART_CARD 60 214 #define SRST_SMART_CARD 60
206 #define SRST_CPU_PERI 61 215 #define SRST_CPU_PERI 61
207 #define SRST_EMEM_PERI 62 216 #define SRST_EMEM_PERI 62
208 #define SRST_USB_PERI 63 217 #define SRST_USB_PERI 63
209 218
210 #define SRST_DMA 64 219 #define SRST_DMA 64
211 #define SRST_GPS 67 220 #define SRST_GPS 67
212 #define SRST_NANDC 68 221 #define SRST_NANDC 68
213 #define SRST_USBOTG0 69 222 #define SRST_USBOTG0 69
214 #define SRST_OTGC0 71 223 #define SRST_OTGC0 71
215 #define SRST_USBOTG1 72 224 #define SRST_USBOTG1 72
216 #define SRST_OTGC1 74 225 #define SRST_OTGC1 74
217 #define SRST_DDRMSCH 79 226 #define SRST_DDRMSCH 79
218 227
219 #define SRST_SDMMC 81 228 #define SRST_SDMMC 81
220 #define SRST_SDIO 82 229 #define SRST_SDIO 82
221 #define SRST_EMMC 83 230 #define SRST_EMMC 83
222 #define SRST_SPI 84 231 #define SRST_SPI 84
223 #define SRST_WDT 86 232 #define SRST_WDT 86
224 #define SRST_SARADC 87 233 #define SRST_SARADC 87
225 #define SRST_DDRPHY 88 234 #define SRST_DDRPHY 88
226 #define SRST_DDRPHY_P 89 235 #define SRST_DDRPHY_P 89
227 #define SRST_DDRCTRL 90 236 #define SRST_DDRCTRL 90
228 #define SRST_DDRCTRL_P 91 237 #define SRST_DDRCTRL_P 91
229 #define SRST_TSP 92 238 #define SRST_TSP 92
230 #define SRST_TSP_CLKIN 93 239 #define SRST_TSP_CLKIN 93
231 #define SRST_HOST0_ECHI 94 240 #define SRST_HOST0_ECHI 94
232 241
233 #define SRST_HDMI_P 96 242 #define SRST_HDMI_P 96
234 #define SRST_VIO_ARBI_H 97 243 #define SRST_VIO_ARBI_H 97
235 #define SRST_VIO0_A 98 244 #define SRST_VIO0_A 98
236 #define SRST_VIO_BUS_H 99 245 #define SRST_VIO_BUS_H 99
237 #define SRST_VOP_A 100 246 #define SRST_VOP_A 100
238 #define SRST_VOP_H 101 247 #define SRST_VOP_H 101
239 #define SRST_VOP_D 102 248 #define SRST_VOP_D 102
240 #define SRST_UTMI0 103 249 #define SRST_UTMI0 103
241 #define SRST_UTMI1 104 250 #define SRST_UTMI1 104
242 #define SRST_USBPOR 105 251 #define SRST_USBPOR 105
243 #define SRST_IEP_A 106 252 #define SRST_IEP_A 106
244 #define SRST_IEP_H 107 253 #define SRST_IEP_H 107
245 #define SRST_RGA_A 108 254 #define SRST_RGA_A 108
246 #define SRST_RGA_H 109 255 #define SRST_RGA_H 109
247 #define SRST_CIF0 110 256 #define SRST_CIF0 110
248 #define SRST_PMU 111 257 #define SRST_PMU 111
249 258
250 #define SRST_VCODEC_A 112 259 #define SRST_VCODEC_A 112
251 #define SRST_VCODEC_H 113 260 #define SRST_VCODEC_H 113
252 #define SRST_VIO1_A 114 261 #define SRST_VIO1_A 114
253 #define SRST_HEVC_CORE 115 262 #define SRST_HEVC_CORE 115
254 #define SRST_VCODEC_NIU_A 116 263 #define SRST_VCODEC_NIU_A 116
255 #define SRST_PMU_NIU_P 117 264 #define SRST_PMU_NIU_P 117
256 #define SRST_LCDC0_S 119 265 #define SRST_LCDC0_S 119
257 #define SRST_GPU 120 266 #define SRST_GPU 120
258 #define SRST_GPU_NIU_A 122 267 #define SRST_GPU_NIU_A 122
259 #define SRST_EBC_A 123 268 #define SRST_EBC_A 123
260 #define SRST_EBC_H 124 269 #define SRST_EBC_H 124
261 270
262 #define SRST_CORE_DBG 128 271 #define SRST_CORE_DBG 128
263 #define SRST_DBG_P 129 272 #define SRST_DBG_P 129
264 #define SRST_TIMER0 130 273 #define SRST_TIMER0 130
265 #define SRST_TIMER1 131 274 #define SRST_TIMER1 131
266 #define SRST_TIMER2 132 275 #define SRST_TIMER2 132
267 #define SRST_TIMER3 133 276 #define SRST_TIMER3 133
268 #define SRST_TIMER4 134 277 #define SRST_TIMER4 134
269 #define SRST_TIMER5 135 278 #define SRST_TIMER5 135
270 #define SRST_VIO_H2P 136 279 #define SRST_VIO_H2P 136
271 #define SRST_VIO_MIPI_DSI 137 280 #define SRST_VIO_MIPI_DSI 137
272 281
273 #endif 282 #endif
274 283
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