1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMO 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMO 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
9 18
10 /* core clocks from */ 19 /* core clocks from */
11 #define PLL_APLL 1 20 #define PLL_APLL 1
12 #define PLL_DPLL 2 21 #define PLL_DPLL 2
13 #define PLL_CPLL 3 22 #define PLL_CPLL 3
14 #define PLL_GPLL 4 23 #define PLL_GPLL 4
15 #define CORE_PERI 5 24 #define CORE_PERI 5
16 #define CORE_L2C 6 25 #define CORE_L2C 6
17 #define ARMCLK 7 26 #define ARMCLK 7
18 27
19 /* sclk gates (special clocks) */ 28 /* sclk gates (special clocks) */
20 #define SCLK_UART0 64 29 #define SCLK_UART0 64
21 #define SCLK_UART1 65 30 #define SCLK_UART1 65
22 #define SCLK_UART2 66 31 #define SCLK_UART2 66
23 #define SCLK_UART3 67 32 #define SCLK_UART3 67
24 #define SCLK_MAC 68 33 #define SCLK_MAC 68
25 #define SCLK_SPI0 69 34 #define SCLK_SPI0 69
26 #define SCLK_SPI1 70 35 #define SCLK_SPI1 70
27 #define SCLK_SARADC 71 36 #define SCLK_SARADC 71
28 #define SCLK_SDMMC 72 37 #define SCLK_SDMMC 72
29 #define SCLK_SDIO 73 38 #define SCLK_SDIO 73
30 #define SCLK_EMMC 74 39 #define SCLK_EMMC 74
31 #define SCLK_I2S0 75 40 #define SCLK_I2S0 75
32 #define SCLK_I2S1 76 41 #define SCLK_I2S1 76
33 #define SCLK_I2S2 77 42 #define SCLK_I2S2 77
34 #define SCLK_SPDIF 78 43 #define SCLK_SPDIF 78
35 #define SCLK_CIF0 79 44 #define SCLK_CIF0 79
36 #define SCLK_CIF1 80 45 #define SCLK_CIF1 80
37 #define SCLK_OTGPHY0 81 46 #define SCLK_OTGPHY0 81
38 #define SCLK_OTGPHY1 82 47 #define SCLK_OTGPHY1 82
39 #define SCLK_HSADC 83 48 #define SCLK_HSADC 83
40 #define SCLK_TIMER0 84 49 #define SCLK_TIMER0 84
41 #define SCLK_TIMER1 85 50 #define SCLK_TIMER1 85
42 #define SCLK_TIMER2 86 51 #define SCLK_TIMER2 86
43 #define SCLK_TIMER3 87 52 #define SCLK_TIMER3 87
44 #define SCLK_TIMER4 88 53 #define SCLK_TIMER4 88
45 #define SCLK_TIMER5 89 54 #define SCLK_TIMER5 89
46 #define SCLK_TIMER6 90 55 #define SCLK_TIMER6 90
47 #define SCLK_JTAG 91 56 #define SCLK_JTAG 91
48 #define SCLK_SMC 92 57 #define SCLK_SMC 92
49 #define SCLK_TSADC 93 58 #define SCLK_TSADC 93
50 59
51 #define DCLK_LCDC0 190 60 #define DCLK_LCDC0 190
52 #define DCLK_LCDC1 191 61 #define DCLK_LCDC1 191
53 62
54 /* aclk gates */ 63 /* aclk gates */
55 #define ACLK_DMA1 192 64 #define ACLK_DMA1 192
56 #define ACLK_DMA2 193 65 #define ACLK_DMA2 193
57 #define ACLK_GPS 194 66 #define ACLK_GPS 194
58 #define ACLK_LCDC0 195 67 #define ACLK_LCDC0 195
59 #define ACLK_LCDC1 196 68 #define ACLK_LCDC1 196
60 #define ACLK_GPU 197 69 #define ACLK_GPU 197
61 #define ACLK_SMC 198 70 #define ACLK_SMC 198
62 #define ACLK_CIF1 199 71 #define ACLK_CIF1 199
63 #define ACLK_IPP 200 72 #define ACLK_IPP 200
64 #define ACLK_RGA 201 73 #define ACLK_RGA 201
65 #define ACLK_CIF0 202 74 #define ACLK_CIF0 202
66 #define ACLK_CPU 203 75 #define ACLK_CPU 203
67 #define ACLK_PERI 204 76 #define ACLK_PERI 204
68 #define ACLK_VEPU 205 77 #define ACLK_VEPU 205
69 #define ACLK_VDPU 206 78 #define ACLK_VDPU 206
70 79
71 /* pclk gates */ 80 /* pclk gates */
72 #define PCLK_GRF 320 81 #define PCLK_GRF 320
73 #define PCLK_PMU 321 82 #define PCLK_PMU 321
74 #define PCLK_TIMER0 322 83 #define PCLK_TIMER0 322
75 #define PCLK_TIMER1 323 84 #define PCLK_TIMER1 323
76 #define PCLK_TIMER2 324 85 #define PCLK_TIMER2 324
77 #define PCLK_TIMER3 325 86 #define PCLK_TIMER3 325
78 #define PCLK_PWM01 326 87 #define PCLK_PWM01 326
79 #define PCLK_PWM23 327 88 #define PCLK_PWM23 327
80 #define PCLK_SPI0 328 89 #define PCLK_SPI0 328
81 #define PCLK_SPI1 329 90 #define PCLK_SPI1 329
82 #define PCLK_SARADC 330 91 #define PCLK_SARADC 330
83 #define PCLK_WDT 331 92 #define PCLK_WDT 331
84 #define PCLK_UART0 332 93 #define PCLK_UART0 332
85 #define PCLK_UART1 333 94 #define PCLK_UART1 333
86 #define PCLK_UART2 334 95 #define PCLK_UART2 334
87 #define PCLK_UART3 335 96 #define PCLK_UART3 335
88 #define PCLK_I2C0 336 97 #define PCLK_I2C0 336
89 #define PCLK_I2C1 337 98 #define PCLK_I2C1 337
90 #define PCLK_I2C2 338 99 #define PCLK_I2C2 338
91 #define PCLK_I2C3 339 100 #define PCLK_I2C3 339
92 #define PCLK_I2C4 340 101 #define PCLK_I2C4 340
93 #define PCLK_GPIO0 341 102 #define PCLK_GPIO0 341
94 #define PCLK_GPIO1 342 103 #define PCLK_GPIO1 342
95 #define PCLK_GPIO2 343 104 #define PCLK_GPIO2 343
96 #define PCLK_GPIO3 344 105 #define PCLK_GPIO3 344
97 #define PCLK_GPIO4 345 106 #define PCLK_GPIO4 345
98 #define PCLK_GPIO6 346 107 #define PCLK_GPIO6 346
99 #define PCLK_EFUSE 347 108 #define PCLK_EFUSE 347
100 #define PCLK_TZPC 348 109 #define PCLK_TZPC 348
101 #define PCLK_TSADC 349 110 #define PCLK_TSADC 349
102 #define PCLK_CPU 350 111 #define PCLK_CPU 350
103 #define PCLK_PERI 351 112 #define PCLK_PERI 351
104 #define PCLK_DDRUPCTL 352 113 #define PCLK_DDRUPCTL 352
105 #define PCLK_PUBL 353 114 #define PCLK_PUBL 353
106 115
107 /* hclk gates */ 116 /* hclk gates */
108 #define HCLK_SDMMC 448 117 #define HCLK_SDMMC 448
109 #define HCLK_SDIO 449 118 #define HCLK_SDIO 449
110 #define HCLK_EMMC 450 119 #define HCLK_EMMC 450
111 #define HCLK_OTG0 451 120 #define HCLK_OTG0 451
112 #define HCLK_EMAC 452 121 #define HCLK_EMAC 452
113 #define HCLK_SPDIF 453 122 #define HCLK_SPDIF 453
114 #define HCLK_I2S0 454 123 #define HCLK_I2S0 454
115 #define HCLK_I2S1 455 124 #define HCLK_I2S1 455
116 #define HCLK_I2S2 456 125 #define HCLK_I2S2 456
117 #define HCLK_OTG1 457 126 #define HCLK_OTG1 457
118 #define HCLK_HSIC 458 127 #define HCLK_HSIC 458
119 #define HCLK_HSADC 459 128 #define HCLK_HSADC 459
120 #define HCLK_PIDF 460 129 #define HCLK_PIDF 460
121 #define HCLK_LCDC0 461 130 #define HCLK_LCDC0 461
122 #define HCLK_LCDC1 462 131 #define HCLK_LCDC1 462
123 #define HCLK_ROM 463 132 #define HCLK_ROM 463
124 #define HCLK_CIF0 464 133 #define HCLK_CIF0 464
125 #define HCLK_IPP 465 134 #define HCLK_IPP 465
126 #define HCLK_RGA 466 135 #define HCLK_RGA 466
127 #define HCLK_NANDC0 467 136 #define HCLK_NANDC0 467
128 #define HCLK_CPU 468 137 #define HCLK_CPU 468
129 #define HCLK_PERI 469 138 #define HCLK_PERI 469
130 #define HCLK_CIF1 470 139 #define HCLK_CIF1 470
131 #define HCLK_VEPU 471 140 #define HCLK_VEPU 471
132 #define HCLK_VDPU 472 141 #define HCLK_VDPU 472
133 #define HCLK_HDMI 473 !! 142
>> 143 #define CLK_NR_CLKS (HCLK_VDPU + 1)
134 144
135 /* soft-reset indices */ 145 /* soft-reset indices */
136 #define SRST_MCORE 2 146 #define SRST_MCORE 2
137 #define SRST_CORE0 3 147 #define SRST_CORE0 3
138 #define SRST_CORE1 4 148 #define SRST_CORE1 4
139 #define SRST_MCORE_DBG 7 149 #define SRST_MCORE_DBG 7
140 #define SRST_CORE0_DBG 8 150 #define SRST_CORE0_DBG 8
141 #define SRST_CORE1_DBG 9 151 #define SRST_CORE1_DBG 9
142 #define SRST_CORE0_WDT 12 152 #define SRST_CORE0_WDT 12
143 #define SRST_CORE1_WDT 13 153 #define SRST_CORE1_WDT 13
144 #define SRST_STRC_SYS 14 154 #define SRST_STRC_SYS 14
145 #define SRST_L2C 15 155 #define SRST_L2C 15
146 156
147 #define SRST_CPU_AHB 17 157 #define SRST_CPU_AHB 17
148 #define SRST_AHB2APB 19 158 #define SRST_AHB2APB 19
149 #define SRST_DMA1 20 159 #define SRST_DMA1 20
150 #define SRST_INTMEM 21 160 #define SRST_INTMEM 21
151 #define SRST_ROM 22 161 #define SRST_ROM 22
152 #define SRST_SPDIF 26 162 #define SRST_SPDIF 26
153 #define SRST_TIMER0 27 163 #define SRST_TIMER0 27
154 #define SRST_TIMER1 28 164 #define SRST_TIMER1 28
155 #define SRST_EFUSE 30 165 #define SRST_EFUSE 30
156 166
157 #define SRST_GPIO0 32 167 #define SRST_GPIO0 32
158 #define SRST_GPIO1 33 168 #define SRST_GPIO1 33
159 #define SRST_GPIO2 34 169 #define SRST_GPIO2 34
160 #define SRST_GPIO3 35 170 #define SRST_GPIO3 35
161 171
162 #define SRST_UART0 39 172 #define SRST_UART0 39
163 #define SRST_UART1 40 173 #define SRST_UART1 40
164 #define SRST_UART2 41 174 #define SRST_UART2 41
165 #define SRST_UART3 42 175 #define SRST_UART3 42
166 #define SRST_I2C0 43 176 #define SRST_I2C0 43
167 #define SRST_I2C1 44 177 #define SRST_I2C1 44
168 #define SRST_I2C2 45 178 #define SRST_I2C2 45
169 #define SRST_I2C3 46 179 #define SRST_I2C3 46
170 #define SRST_I2C4 47 180 #define SRST_I2C4 47
171 181
172 #define SRST_PWM0 48 182 #define SRST_PWM0 48
173 #define SRST_PWM1 49 183 #define SRST_PWM1 49
174 #define SRST_DAP_PO 50 184 #define SRST_DAP_PO 50
175 #define SRST_DAP 51 185 #define SRST_DAP 51
176 #define SRST_DAP_SYS 52 186 #define SRST_DAP_SYS 52
177 #define SRST_TPIU_ATB 53 187 #define SRST_TPIU_ATB 53
178 #define SRST_PMU_APB 54 188 #define SRST_PMU_APB 54
179 #define SRST_GRF 55 189 #define SRST_GRF 55
180 #define SRST_PMU 56 190 #define SRST_PMU 56
181 #define SRST_PERI_AXI 57 191 #define SRST_PERI_AXI 57
182 #define SRST_PERI_AHB 58 192 #define SRST_PERI_AHB 58
183 #define SRST_PERI_APB 59 193 #define SRST_PERI_APB 59
184 #define SRST_PERI_NIU 60 194 #define SRST_PERI_NIU 60
185 #define SRST_CPU_PERI 61 195 #define SRST_CPU_PERI 61
186 #define SRST_EMEM_PERI 62 196 #define SRST_EMEM_PERI 62
187 #define SRST_USB_PERI 63 197 #define SRST_USB_PERI 63
188 198
189 #define SRST_DMA2 64 199 #define SRST_DMA2 64
190 #define SRST_SMC 65 200 #define SRST_SMC 65
191 #define SRST_MAC 66 201 #define SRST_MAC 66
192 #define SRST_NANC0 68 202 #define SRST_NANC0 68
193 #define SRST_USBOTG0 69 203 #define SRST_USBOTG0 69
194 #define SRST_USBPHY0 70 204 #define SRST_USBPHY0 70
195 #define SRST_OTGC0 71 205 #define SRST_OTGC0 71
196 #define SRST_USBOTG1 72 206 #define SRST_USBOTG1 72
197 #define SRST_USBPHY1 73 207 #define SRST_USBPHY1 73
198 #define SRST_OTGC1 74 208 #define SRST_OTGC1 74
199 #define SRST_HSADC 76 209 #define SRST_HSADC 76
200 #define SRST_PIDFILTER 77 210 #define SRST_PIDFILTER 77
201 #define SRST_DDR_MSCH 79 211 #define SRST_DDR_MSCH 79
202 212
203 #define SRST_TZPC 80 213 #define SRST_TZPC 80
204 #define SRST_SDMMC 81 214 #define SRST_SDMMC 81
205 #define SRST_SDIO 82 215 #define SRST_SDIO 82
206 #define SRST_EMMC 83 216 #define SRST_EMMC 83
207 #define SRST_SPI0 84 217 #define SRST_SPI0 84
208 #define SRST_SPI1 85 218 #define SRST_SPI1 85
209 #define SRST_WDT 86 219 #define SRST_WDT 86
210 #define SRST_SARADC 87 220 #define SRST_SARADC 87
211 #define SRST_DDRPHY 88 221 #define SRST_DDRPHY 88
212 #define SRST_DDRPHY_APB 89 222 #define SRST_DDRPHY_APB 89
213 #define SRST_DDRCTL 90 223 #define SRST_DDRCTL 90
214 #define SRST_DDRCTL_APB 91 224 #define SRST_DDRCTL_APB 91
215 #define SRST_DDRPUB 93 225 #define SRST_DDRPUB 93
216 226
217 #define SRST_VIO0_AXI 98 227 #define SRST_VIO0_AXI 98
218 #define SRST_VIO0_AHB 99 228 #define SRST_VIO0_AHB 99
219 #define SRST_LCDC0_AXI 100 229 #define SRST_LCDC0_AXI 100
220 #define SRST_LCDC0_AHB 101 230 #define SRST_LCDC0_AHB 101
221 #define SRST_LCDC0_DCLK 102 231 #define SRST_LCDC0_DCLK 102
222 #define SRST_LCDC1_AXI 103 232 #define SRST_LCDC1_AXI 103
223 #define SRST_LCDC1_AHB 104 233 #define SRST_LCDC1_AHB 104
224 #define SRST_LCDC1_DCLK 105 234 #define SRST_LCDC1_DCLK 105
225 #define SRST_IPP_AXI 106 235 #define SRST_IPP_AXI 106
226 #define SRST_IPP_AHB 107 236 #define SRST_IPP_AHB 107
227 #define SRST_RGA_AXI 108 237 #define SRST_RGA_AXI 108
228 #define SRST_RGA_AHB 109 238 #define SRST_RGA_AHB 109
229 #define SRST_CIF0 110 239 #define SRST_CIF0 110
230 240
231 #define SRST_VCODEC_AXI 112 241 #define SRST_VCODEC_AXI 112
232 #define SRST_VCODEC_AHB 113 242 #define SRST_VCODEC_AHB 113
233 #define SRST_VIO1_AXI 114 243 #define SRST_VIO1_AXI 114
234 #define SRST_VCODEC_CPU 115 244 #define SRST_VCODEC_CPU 115
235 #define SRST_VCODEC_NIU 116 245 #define SRST_VCODEC_NIU 116
236 #define SRST_GPU 120 246 #define SRST_GPU 120
237 #define SRST_GPU_NIU 122 247 #define SRST_GPU_NIU 122
238 #define SRST_TFUN_ATB 125 248 #define SRST_TFUN_ATB 125
239 #define SRST_TFUN_APB 126 249 #define SRST_TFUN_APB 126
240 #define SRST_CTI4_APB 127 250 #define SRST_CTI4_APB 127
241 251
242 #define SRST_TPIU_APB 128 252 #define SRST_TPIU_APB 128
243 #define SRST_TRACE 129 253 #define SRST_TRACE 129
244 #define SRST_CORE_DBG 130 254 #define SRST_CORE_DBG 130
245 #define SRST_DBG_APB 131 255 #define SRST_DBG_APB 131
246 #define SRST_CTI0 132 256 #define SRST_CTI0 132
247 #define SRST_CTI0_APB 133 257 #define SRST_CTI0_APB 133
248 #define SRST_CTI1 134 258 #define SRST_CTI1 134
249 #define SRST_CTI1_APB 135 259 #define SRST_CTI1_APB 135
250 #define SRST_PTM_CORE0 136 260 #define SRST_PTM_CORE0 136
251 #define SRST_PTM_CORE1 137 261 #define SRST_PTM_CORE1 137
252 #define SRST_PTM0 138 262 #define SRST_PTM0 138
253 #define SRST_PTM0_ATB 139 263 #define SRST_PTM0_ATB 139
254 #define SRST_PTM1 140 264 #define SRST_PTM1 140
255 #define SRST_PTM1_ATB 141 265 #define SRST_PTM1_ATB 141
256 #define SRST_CTM 142 266 #define SRST_CTM 142
257 #define SRST_TS 143 267 #define SRST_TS 143
258 268
259 #endif 269 #endif
260 270
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