1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
9 18
10 #include <dt-bindings/clock/rk3188-cru-common. 19 #include <dt-bindings/clock/rk3188-cru-common.h>
11 20
12 /* soft-reset indices */ 21 /* soft-reset indices */
13 #define SRST_PTM_CORE2 0 22 #define SRST_PTM_CORE2 0
14 #define SRST_PTM_CORE3 1 23 #define SRST_PTM_CORE3 1
15 #define SRST_CORE2 5 24 #define SRST_CORE2 5
16 #define SRST_CORE3 6 25 #define SRST_CORE3 6
17 #define SRST_CORE2_DBG 10 26 #define SRST_CORE2_DBG 10
18 #define SRST_CORE3_DBG 11 27 #define SRST_CORE3_DBG 11
19 28
20 #define SRST_TIMER2 16 29 #define SRST_TIMER2 16
21 #define SRST_TIMER4 23 30 #define SRST_TIMER4 23
22 #define SRST_I2S0 24 31 #define SRST_I2S0 24
23 #define SRST_TIMER5 25 32 #define SRST_TIMER5 25
24 #define SRST_TIMER3 29 33 #define SRST_TIMER3 29
25 #define SRST_TIMER6 31 34 #define SRST_TIMER6 31
26 35
27 #define SRST_PTM3 36 36 #define SRST_PTM3 36
28 #define SRST_PTM3_ATB 37 37 #define SRST_PTM3_ATB 37
29 38
30 #define SRST_GPS 67 39 #define SRST_GPS 67
31 #define SRST_HSICPHY 75 40 #define SRST_HSICPHY 75
32 #define SRST_TIMER 78 41 #define SRST_TIMER 78
33 42
34 #define SRST_PTM2 92 43 #define SRST_PTM2 92
35 #define SRST_CORE2_WDT 94 44 #define SRST_CORE2_WDT 94
36 #define SRST_CORE3_WDT 95 45 #define SRST_CORE3_WDT 95
37 46
38 #define SRST_PTM2_ATB 111 47 #define SRST_PTM2_ATB 111
39 48
40 #define SRST_HSIC 117 49 #define SRST_HSIC 117
41 #define SRST_CTI2 118 50 #define SRST_CTI2 118
42 #define SRST_CTI2_APB 119 51 #define SRST_CTI2_APB 119
43 #define SRST_GPU_BRIDGE 121 52 #define SRST_GPU_BRIDGE 121
44 #define SRST_CTI3 123 53 #define SRST_CTI3 123
45 #define SRST_CTI3_APB 124 54 #define SRST_CTI3_APB 124
46 55
47 #endif 56 #endif
48 57
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