1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 5 */ 6 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H 9 9 10 #include <dt-bindings/clock/rk3188-cru-common. 10 #include <dt-bindings/clock/rk3188-cru-common.h> 11 11 12 /* soft-reset indices */ 12 /* soft-reset indices */ 13 #define SRST_PTM_CORE2 0 13 #define SRST_PTM_CORE2 0 14 #define SRST_PTM_CORE3 1 14 #define SRST_PTM_CORE3 1 15 #define SRST_CORE2 5 15 #define SRST_CORE2 5 16 #define SRST_CORE3 6 16 #define SRST_CORE3 6 17 #define SRST_CORE2_DBG 10 17 #define SRST_CORE2_DBG 10 18 #define SRST_CORE3_DBG 11 18 #define SRST_CORE3_DBG 11 19 19 20 #define SRST_TIMER2 16 20 #define SRST_TIMER2 16 21 #define SRST_TIMER4 23 21 #define SRST_TIMER4 23 22 #define SRST_I2S0 24 22 #define SRST_I2S0 24 23 #define SRST_TIMER5 25 23 #define SRST_TIMER5 25 24 #define SRST_TIMER3 29 24 #define SRST_TIMER3 29 25 #define SRST_TIMER6 31 25 #define SRST_TIMER6 31 26 26 27 #define SRST_PTM3 36 27 #define SRST_PTM3 36 28 #define SRST_PTM3_ATB 37 28 #define SRST_PTM3_ATB 37 29 29 30 #define SRST_GPS 67 30 #define SRST_GPS 67 31 #define SRST_HSICPHY 75 31 #define SRST_HSICPHY 75 32 #define SRST_TIMER 78 32 #define SRST_TIMER 78 33 33 34 #define SRST_PTM2 92 34 #define SRST_PTM2 92 35 #define SRST_CORE2_WDT 94 35 #define SRST_CORE2_WDT 94 36 #define SRST_CORE3_WDT 95 36 #define SRST_CORE3_WDT 95 37 37 38 #define SRST_PTM2_ATB 111 38 #define SRST_PTM2_ATB 111 39 39 40 #define SRST_HSIC 117 40 #define SRST_HSIC 117 41 #define SRST_CTI2 118 41 #define SRST_CTI2 118 42 #define SRST_CTI2_APB 119 42 #define SRST_CTI2_APB 119 43 #define SRST_GPU_BRIDGE 121 43 #define SRST_GPU_BRIDGE 121 44 #define SRST_CTI3 123 44 #define SRST_CTI3 123 45 #define SRST_CTI3_APB 124 45 #define SRST_CTI3_APB 124 46 46 47 #endif 47 #endif 48 48
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