1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2015 Rockchip Electronics Co. 2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
4 * Author: Jeffy Chen <jeffy.chen@rock-chips.c 3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
9 18
10 /* core clocks */ 19 /* core clocks */
11 #define PLL_APLL 1 20 #define PLL_APLL 1
12 #define PLL_DPLL 2 21 #define PLL_DPLL 2
13 #define PLL_CPLL 3 22 #define PLL_CPLL 3
14 #define PLL_GPLL 4 23 #define PLL_GPLL 4
15 #define ARMCLK 5 24 #define ARMCLK 5
16 25
17 /* sclk gates (special clocks) */ 26 /* sclk gates (special clocks) */
18 #define SCLK_SPI0 65 27 #define SCLK_SPI0 65
19 #define SCLK_NANDC 67 28 #define SCLK_NANDC 67
20 #define SCLK_SDMMC 68 29 #define SCLK_SDMMC 68
21 #define SCLK_SDIO 69 30 #define SCLK_SDIO 69
22 #define SCLK_EMMC 71 31 #define SCLK_EMMC 71
23 #define SCLK_TSADC 72 32 #define SCLK_TSADC 72
24 #define SCLK_UART0 77 33 #define SCLK_UART0 77
25 #define SCLK_UART1 78 34 #define SCLK_UART1 78
26 #define SCLK_UART2 79 35 #define SCLK_UART2 79
27 #define SCLK_I2S0 80 36 #define SCLK_I2S0 80
28 #define SCLK_I2S1 81 37 #define SCLK_I2S1 81
29 #define SCLK_I2S2 82 38 #define SCLK_I2S2 82
30 #define SCLK_SPDIF 83 39 #define SCLK_SPDIF 83
31 #define SCLK_TIMER0 85 40 #define SCLK_TIMER0 85
32 #define SCLK_TIMER1 86 41 #define SCLK_TIMER1 86
33 #define SCLK_TIMER2 87 42 #define SCLK_TIMER2 87
34 #define SCLK_TIMER3 88 43 #define SCLK_TIMER3 88
35 #define SCLK_TIMER4 89 44 #define SCLK_TIMER4 89
36 #define SCLK_TIMER5 90 45 #define SCLK_TIMER5 90
37 #define SCLK_I2S_OUT 113 46 #define SCLK_I2S_OUT 113
38 #define SCLK_SDMMC_DRV 114 47 #define SCLK_SDMMC_DRV 114
39 #define SCLK_SDIO_DRV 115 48 #define SCLK_SDIO_DRV 115
40 #define SCLK_EMMC_DRV 117 49 #define SCLK_EMMC_DRV 117
41 #define SCLK_SDMMC_SAMPLE 118 50 #define SCLK_SDMMC_SAMPLE 118
42 #define SCLK_SDIO_SAMPLE 119 51 #define SCLK_SDIO_SAMPLE 119
43 #define SCLK_SDIO_SRC 120 <<
44 #define SCLK_EMMC_SAMPLE 121 52 #define SCLK_EMMC_SAMPLE 121
45 #define SCLK_VOP 122 53 #define SCLK_VOP 122
46 #define SCLK_HDMI_HDCP 123 54 #define SCLK_HDMI_HDCP 123
47 #define SCLK_MAC_SRC 124 55 #define SCLK_MAC_SRC 124
48 #define SCLK_MAC_EXTCLK 125 56 #define SCLK_MAC_EXTCLK 125
49 #define SCLK_MAC 126 57 #define SCLK_MAC 126
50 #define SCLK_MAC_REFOUT 127 58 #define SCLK_MAC_REFOUT 127
51 #define SCLK_MAC_REF 128 59 #define SCLK_MAC_REF 128
52 #define SCLK_MAC_RX 129 60 #define SCLK_MAC_RX 129
53 #define SCLK_MAC_TX 130 61 #define SCLK_MAC_TX 130
54 #define SCLK_MAC_PHY 131 62 #define SCLK_MAC_PHY 131
55 #define SCLK_MAC_OUT 132 63 #define SCLK_MAC_OUT 132
56 #define SCLK_VDEC_CABAC 133 <<
57 #define SCLK_VDEC_CORE 134 <<
58 #define SCLK_RGA 135 <<
59 #define SCLK_HDCP 136 <<
60 #define SCLK_HDMI_CEC 137 <<
61 #define SCLK_CRYPTO 138 <<
62 #define SCLK_TSP 139 <<
63 #define SCLK_HSADC 140 <<
64 #define SCLK_WIFI 141 <<
65 #define SCLK_OTGPHY0 142 <<
66 #define SCLK_OTGPHY1 143 <<
67 #define SCLK_HDMI_PHY 144 <<
68 64
69 /* dclk gates */ 65 /* dclk gates */
70 #define DCLK_VOP 190 66 #define DCLK_VOP 190
71 #define DCLK_HDMI_PHY 191 67 #define DCLK_HDMI_PHY 191
72 68
73 /* aclk gates */ 69 /* aclk gates */
74 #define ACLK_DMAC 194 70 #define ACLK_DMAC 194
75 #define ACLK_CPU 195 <<
76 #define ACLK_VPU_PRE 196 <<
77 #define ACLK_RKVDEC_PRE 197 <<
78 #define ACLK_RGA_PRE 198 <<
79 #define ACLK_IEP_PRE 199 <<
80 #define ACLK_HDCP_PRE 200 <<
81 #define ACLK_VOP_PRE 201 <<
82 #define ACLK_VPU 202 <<
83 #define ACLK_RKVDEC 203 <<
84 #define ACLK_IEP 204 <<
85 #define ACLK_RGA 205 <<
86 #define ACLK_HDCP 206 <<
87 #define ACLK_PERI 210 71 #define ACLK_PERI 210
88 #define ACLK_VOP 211 72 #define ACLK_VOP 211
89 #define ACLK_GMAC 212 73 #define ACLK_GMAC 212
90 #define ACLK_GPU 213 <<
91 74
92 /* pclk gates */ 75 /* pclk gates */
93 #define PCLK_GPIO0 320 76 #define PCLK_GPIO0 320
94 #define PCLK_GPIO1 321 77 #define PCLK_GPIO1 321
95 #define PCLK_GPIO2 322 78 #define PCLK_GPIO2 322
96 #define PCLK_GPIO3 323 79 #define PCLK_GPIO3 323
97 #define PCLK_VIO_H2P 324 <<
98 #define PCLK_HDCP 325 <<
99 #define PCLK_EFUSE_1024 326 <<
100 #define PCLK_EFUSE_256 327 <<
101 #define PCLK_GRF 329 80 #define PCLK_GRF 329
102 #define PCLK_I2C0 332 81 #define PCLK_I2C0 332
103 #define PCLK_I2C1 333 82 #define PCLK_I2C1 333
104 #define PCLK_I2C2 334 83 #define PCLK_I2C2 334
105 #define PCLK_I2C3 335 84 #define PCLK_I2C3 335
106 #define PCLK_SPI0 338 85 #define PCLK_SPI0 338
107 #define PCLK_UART0 341 86 #define PCLK_UART0 341
108 #define PCLK_UART1 342 87 #define PCLK_UART1 342
109 #define PCLK_UART2 343 88 #define PCLK_UART2 343
110 #define PCLK_TSADC 344 89 #define PCLK_TSADC 344
111 #define PCLK_PWM 350 90 #define PCLK_PWM 350
112 #define PCLK_TIMER 353 91 #define PCLK_TIMER 353
113 #define PCLK_CPU 354 <<
114 #define PCLK_PERI 363 92 #define PCLK_PERI 363
115 #define PCLK_HDMI_CTRL 364 93 #define PCLK_HDMI_CTRL 364
116 #define PCLK_HDMI_PHY 365 94 #define PCLK_HDMI_PHY 365
117 #define PCLK_GMAC 367 95 #define PCLK_GMAC 367
118 96
119 /* hclk gates */ 97 /* hclk gates */
120 #define HCLK_I2S0_8CH 442 98 #define HCLK_I2S0_8CH 442
121 #define HCLK_I2S1_8CH 443 99 #define HCLK_I2S1_8CH 443
122 #define HCLK_I2S2_2CH 444 100 #define HCLK_I2S2_2CH 444
123 #define HCLK_SPDIF_8CH 445 101 #define HCLK_SPDIF_8CH 445
124 #define HCLK_VOP 452 102 #define HCLK_VOP 452
125 #define HCLK_NANDC 453 103 #define HCLK_NANDC 453
126 #define HCLK_SDMMC 456 104 #define HCLK_SDMMC 456
127 #define HCLK_SDIO 457 105 #define HCLK_SDIO 457
128 #define HCLK_EMMC 459 106 #define HCLK_EMMC 459
129 #define HCLK_CPU 460 <<
130 #define HCLK_VPU_PRE 461 <<
131 #define HCLK_RKVDEC_PRE 462 <<
132 #define HCLK_VIO_PRE 463 <<
133 #define HCLK_VPU 464 <<
134 #define HCLK_RKVDEC 465 <<
135 #define HCLK_VIO 466 <<
136 #define HCLK_RGA 467 <<
137 #define HCLK_IEP 468 <<
138 #define HCLK_VIO_H2P 469 <<
139 #define HCLK_HDCP_MMU 470 <<
140 #define HCLK_HOST0 471 <<
141 #define HCLK_HOST1 472 <<
142 #define HCLK_HOST2 473 <<
143 #define HCLK_OTG 474 <<
144 #define HCLK_TSP 475 <<
145 #define HCLK_M_CRYPTO 476 <<
146 #define HCLK_S_CRYPTO 477 <<
147 #define HCLK_PERI 478 107 #define HCLK_PERI 478
148 108
149 #define CLK_NR_CLKS (HCLK_PERI + 1 109 #define CLK_NR_CLKS (HCLK_PERI + 1)
150 110
151 /* soft-reset indices */ 111 /* soft-reset indices */
152 #define SRST_CORE0_PO 0 112 #define SRST_CORE0_PO 0
153 #define SRST_CORE1_PO 1 113 #define SRST_CORE1_PO 1
154 #define SRST_CORE2_PO 2 114 #define SRST_CORE2_PO 2
155 #define SRST_CORE3_PO 3 115 #define SRST_CORE3_PO 3
156 #define SRST_CORE0 4 116 #define SRST_CORE0 4
157 #define SRST_CORE1 5 117 #define SRST_CORE1 5
158 #define SRST_CORE2 6 118 #define SRST_CORE2 6
159 #define SRST_CORE3 7 119 #define SRST_CORE3 7
160 #define SRST_CORE0_DBG 8 120 #define SRST_CORE0_DBG 8
161 #define SRST_CORE1_DBG 9 121 #define SRST_CORE1_DBG 9
162 #define SRST_CORE2_DBG 10 122 #define SRST_CORE2_DBG 10
163 #define SRST_CORE3_DBG 11 123 #define SRST_CORE3_DBG 11
164 #define SRST_TOPDBG 12 124 #define SRST_TOPDBG 12
165 #define SRST_ACLK_CORE 13 125 #define SRST_ACLK_CORE 13
166 #define SRST_NOC 14 126 #define SRST_NOC 14
167 #define SRST_L2C 15 127 #define SRST_L2C 15
168 128
169 #define SRST_CPUSYS_H 18 129 #define SRST_CPUSYS_H 18
170 #define SRST_BUSSYS_H 19 130 #define SRST_BUSSYS_H 19
171 #define SRST_SPDIF 20 131 #define SRST_SPDIF 20
172 #define SRST_INTMEM 21 132 #define SRST_INTMEM 21
173 #define SRST_ROM 22 133 #define SRST_ROM 22
174 #define SRST_OTG_ADP 23 134 #define SRST_OTG_ADP 23
175 #define SRST_I2S0 24 135 #define SRST_I2S0 24
176 #define SRST_I2S1 25 136 #define SRST_I2S1 25
177 #define SRST_I2S2 26 137 #define SRST_I2S2 26
178 #define SRST_ACODEC_P 27 138 #define SRST_ACODEC_P 27
179 #define SRST_DFIMON 28 139 #define SRST_DFIMON 28
180 #define SRST_MSCH 29 140 #define SRST_MSCH 29
181 #define SRST_EFUSE1024 30 141 #define SRST_EFUSE1024 30
182 #define SRST_EFUSE256 31 142 #define SRST_EFUSE256 31
183 143
184 #define SRST_GPIO0 32 144 #define SRST_GPIO0 32
185 #define SRST_GPIO1 33 145 #define SRST_GPIO1 33
186 #define SRST_GPIO2 34 146 #define SRST_GPIO2 34
187 #define SRST_GPIO3 35 147 #define SRST_GPIO3 35
188 #define SRST_PERIPH_NOC_A 36 148 #define SRST_PERIPH_NOC_A 36
189 #define SRST_PERIPH_NOC_BUS_H 37 149 #define SRST_PERIPH_NOC_BUS_H 37
190 #define SRST_PERIPH_NOC_P 38 150 #define SRST_PERIPH_NOC_P 38
191 #define SRST_UART0 39 151 #define SRST_UART0 39
192 #define SRST_UART1 40 152 #define SRST_UART1 40
193 #define SRST_UART2 41 153 #define SRST_UART2 41
194 #define SRST_PHYNOC 42 154 #define SRST_PHYNOC 42
195 #define SRST_I2C0 43 155 #define SRST_I2C0 43
196 #define SRST_I2C1 44 156 #define SRST_I2C1 44
197 #define SRST_I2C2 45 157 #define SRST_I2C2 45
198 #define SRST_I2C3 46 158 #define SRST_I2C3 46
199 159
200 #define SRST_PWM 48 160 #define SRST_PWM 48
201 #define SRST_A53_GIC 49 161 #define SRST_A53_GIC 49
202 #define SRST_DAP 51 162 #define SRST_DAP 51
203 #define SRST_DAP_NOC 52 163 #define SRST_DAP_NOC 52
204 #define SRST_CRYPTO 53 164 #define SRST_CRYPTO 53
205 #define SRST_SGRF 54 165 #define SRST_SGRF 54
206 #define SRST_GRF 55 166 #define SRST_GRF 55
207 #define SRST_GMAC 56 167 #define SRST_GMAC 56
208 #define SRST_PERIPH_NOC_H 58 168 #define SRST_PERIPH_NOC_H 58
209 #define SRST_MACPHY 63 169 #define SRST_MACPHY 63
210 170
211 #define SRST_DMA 64 171 #define SRST_DMA 64
212 #define SRST_NANDC 68 172 #define SRST_NANDC 68
213 #define SRST_USBOTG 69 173 #define SRST_USBOTG 69
214 #define SRST_OTGC 70 174 #define SRST_OTGC 70
215 #define SRST_USBHOST0 71 175 #define SRST_USBHOST0 71
216 #define SRST_HOST_CTRL0 72 176 #define SRST_HOST_CTRL0 72
217 #define SRST_USBHOST1 73 177 #define SRST_USBHOST1 73
218 #define SRST_HOST_CTRL1 74 178 #define SRST_HOST_CTRL1 74
219 #define SRST_USBHOST2 75 179 #define SRST_USBHOST2 75
220 #define SRST_HOST_CTRL2 76 180 #define SRST_HOST_CTRL2 76
221 #define SRST_USBPOR0 77 181 #define SRST_USBPOR0 77
222 #define SRST_USBPOR1 78 182 #define SRST_USBPOR1 78
223 #define SRST_DDRMSCH 79 183 #define SRST_DDRMSCH 79
224 184
225 #define SRST_SMART_CARD 80 185 #define SRST_SMART_CARD 80
226 #define SRST_SDMMC 81 186 #define SRST_SDMMC 81
227 #define SRST_SDIO 82 187 #define SRST_SDIO 82
228 #define SRST_EMMC 83 188 #define SRST_EMMC 83
229 #define SRST_SPI 84 189 #define SRST_SPI 84
230 #define SRST_TSP_H 85 190 #define SRST_TSP_H 85
231 #define SRST_TSP 86 191 #define SRST_TSP 86
232 #define SRST_TSADC 87 192 #define SRST_TSADC 87
233 #define SRST_DDRPHY 88 193 #define SRST_DDRPHY 88
234 #define SRST_DDRPHY_P 89 194 #define SRST_DDRPHY_P 89
235 #define SRST_DDRCTRL 90 195 #define SRST_DDRCTRL 90
236 #define SRST_DDRCTRL_P 91 196 #define SRST_DDRCTRL_P 91
237 #define SRST_HOST0_ECHI 92 197 #define SRST_HOST0_ECHI 92
238 #define SRST_HOST1_ECHI 93 198 #define SRST_HOST1_ECHI 93
239 #define SRST_HOST2_ECHI 94 199 #define SRST_HOST2_ECHI 94
240 #define SRST_VOP_NOC_A 95 200 #define SRST_VOP_NOC_A 95
241 201
242 #define SRST_HDMI_P 96 202 #define SRST_HDMI_P 96
243 #define SRST_VIO_ARBI_H 97 203 #define SRST_VIO_ARBI_H 97
244 #define SRST_IEP_NOC_A 98 204 #define SRST_IEP_NOC_A 98
245 #define SRST_VIO_NOC_H 99 205 #define SRST_VIO_NOC_H 99
246 #define SRST_VOP_A 100 206 #define SRST_VOP_A 100
247 #define SRST_VOP_H 101 207 #define SRST_VOP_H 101
248 #define SRST_VOP_D 102 208 #define SRST_VOP_D 102
249 #define SRST_UTMI0 103 209 #define SRST_UTMI0 103
250 #define SRST_UTMI1 104 210 #define SRST_UTMI1 104
251 #define SRST_UTMI2 105 211 #define SRST_UTMI2 105
252 #define SRST_UTMI3 106 212 #define SRST_UTMI3 106
253 #define SRST_RGA 107 213 #define SRST_RGA 107
254 #define SRST_RGA_NOC_A 108 214 #define SRST_RGA_NOC_A 108
255 #define SRST_RGA_A 109 215 #define SRST_RGA_A 109
256 #define SRST_RGA_H 110 216 #define SRST_RGA_H 110
257 #define SRST_HDCP_A 111 217 #define SRST_HDCP_A 111
258 218
259 #define SRST_VPU_A 112 219 #define SRST_VPU_A 112
260 #define SRST_VPU_H 113 220 #define SRST_VPU_H 113
261 #define SRST_VPU_NOC_A 116 221 #define SRST_VPU_NOC_A 116
262 #define SRST_VPU_NOC_H 117 222 #define SRST_VPU_NOC_H 117
263 #define SRST_RKVDEC_A 118 223 #define SRST_RKVDEC_A 118
264 #define SRST_RKVDEC_NOC_A 119 224 #define SRST_RKVDEC_NOC_A 119
265 #define SRST_RKVDEC_H 120 225 #define SRST_RKVDEC_H 120
266 #define SRST_RKVDEC_NOC_H 121 226 #define SRST_RKVDEC_NOC_H 121
267 #define SRST_RKVDEC_CORE 122 227 #define SRST_RKVDEC_CORE 122
268 #define SRST_RKVDEC_CABAC 123 228 #define SRST_RKVDEC_CABAC 123
269 #define SRST_IEP_A 124 229 #define SRST_IEP_A 124
270 #define SRST_IEP_H 125 230 #define SRST_IEP_H 125
271 #define SRST_GPU_A 126 231 #define SRST_GPU_A 126
272 #define SRST_GPU_NOC_A 127 232 #define SRST_GPU_NOC_A 127
273 233
274 #define SRST_CORE_DBG 128 234 #define SRST_CORE_DBG 128
275 #define SRST_DBG_P 129 235 #define SRST_DBG_P 129
276 #define SRST_TIMER0 130 236 #define SRST_TIMER0 130
277 #define SRST_TIMER1 131 237 #define SRST_TIMER1 131
278 #define SRST_TIMER2 132 238 #define SRST_TIMER2 132
279 #define SRST_TIMER3 133 239 #define SRST_TIMER3 133
280 #define SRST_TIMER4 134 240 #define SRST_TIMER4 134
281 #define SRST_TIMER5 135 241 #define SRST_TIMER5 135
282 #define SRST_VIO_H2P 136 242 #define SRST_VIO_H2P 136
283 #define SRST_HDMIPHY 139 243 #define SRST_HDMIPHY 139
284 #define SRST_VDAC 140 244 #define SRST_VDAC 140
285 #define SRST_TIMER_6CH_P 141 245 #define SRST_TIMER_6CH_P 141
286 246
287 #endif 247 #endif
288 248
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