1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_GPLL 4 15 #define PLL_NPLL 5 16 #define ARMCLK 6 17 18 /* sclk gates (special clocks) */ 19 #define SCLK_GPU 64 20 #define SCLK_SPI0 65 21 #define SCLK_SPI1 66 22 #define SCLK_SPI2 67 23 #define SCLK_SDMMC 68 24 #define SCLK_SDIO0 69 25 #define SCLK_SDIO1 70 26 #define SCLK_EMMC 71 27 #define SCLK_TSADC 72 28 #define SCLK_SARADC 73 29 #define SCLK_PS2C 74 30 #define SCLK_NANDC0 75 31 #define SCLK_NANDC1 76 32 #define SCLK_UART0 77 33 #define SCLK_UART1 78 34 #define SCLK_UART2 79 35 #define SCLK_UART3 80 36 #define SCLK_UART4 81 37 #define SCLK_I2S0 82 38 #define SCLK_SPDIF 83 39 #define SCLK_SPDIF8CH 84 40 #define SCLK_TIMER0 85 41 #define SCLK_TIMER1 86 42 #define SCLK_TIMER2 87 43 #define SCLK_TIMER3 88 44 #define SCLK_TIMER4 89 45 #define SCLK_TIMER5 90 46 #define SCLK_TIMER6 91 47 #define SCLK_HSADC 92 48 #define SCLK_OTGPHY0 93 49 #define SCLK_OTGPHY1 94 50 #define SCLK_OTGPHY2 95 51 #define SCLK_OTG_ADP 96 52 #define SCLK_HSICPHY480M 97 53 #define SCLK_HSICPHY12M 98 54 #define SCLK_MACREF 99 55 #define SCLK_LCDC_PWM0 100 56 #define SCLK_LCDC_PWM1 101 57 #define SCLK_MAC_RX 102 58 #define SCLK_MAC_TX 103 59 #define SCLK_EDP_24M 104 60 #define SCLK_EDP 105 61 #define SCLK_RGA 106 62 #define SCLK_ISP 107 63 #define SCLK_ISP_JPE 108 64 #define SCLK_HDMI_HDCP 109 65 #define SCLK_HDMI_CEC 110 66 #define SCLK_HEVC_CABAC 111 67 #define SCLK_HEVC_CORE 112 68 #define SCLK_I2S0_OUT 113 69 #define SCLK_SDMMC_DRV 114 70 #define SCLK_SDIO0_DRV 115 71 #define SCLK_SDIO1_DRV 116 72 #define SCLK_EMMC_DRV 117 73 #define SCLK_SDMMC_SAMPLE 118 74 #define SCLK_SDIO0_SAMPLE 119 75 #define SCLK_SDIO1_SAMPLE 120 76 #define SCLK_EMMC_SAMPLE 121 77 #define SCLK_USBPHY480M_SRC 122 78 #define SCLK_PVTM_CORE 123 79 #define SCLK_PVTM_GPU 124 80 #define SCLK_CRYPTO 125 81 #define SCLK_MIPIDSI_24M 126 82 #define SCLK_VIP_OUT 127 83 84 #define SCLK_MAC 151 85 #define SCLK_MACREF_OUT 152 86 87 #define DCLK_VOP0 190 88 #define DCLK_VOP1 191 89 90 /* aclk gates */ 91 #define ACLK_GPU 192 92 #define ACLK_DMAC1 193 93 #define ACLK_DMAC2 194 94 #define ACLK_MMU 195 95 #define ACLK_GMAC 196 96 #define ACLK_VOP0 197 97 #define ACLK_VOP1 198 98 #define ACLK_CRYPTO 199 99 #define ACLK_RGA 200 100 #define ACLK_RGA_NIU 201 101 #define ACLK_IEP 202 102 #define ACLK_VIO0_NIU 203 103 #define ACLK_VIP 204 104 #define ACLK_ISP 205 105 #define ACLK_VIO1_NIU 206 106 #define ACLK_HEVC 207 107 #define ACLK_VCODEC 208 108 #define ACLK_CPU 209 109 #define ACLK_PERI 210 110 111 /* pclk gates */ 112 #define PCLK_GPIO0 320 113 #define PCLK_GPIO1 321 114 #define PCLK_GPIO2 322 115 #define PCLK_GPIO3 323 116 #define PCLK_GPIO4 324 117 #define PCLK_GPIO5 325 118 #define PCLK_GPIO6 326 119 #define PCLK_GPIO7 327 120 #define PCLK_GPIO8 328 121 #define PCLK_GRF 329 122 #define PCLK_SGRF 330 123 #define PCLK_PMU 331 124 #define PCLK_I2C0 332 125 #define PCLK_I2C1 333 126 #define PCLK_I2C2 334 127 #define PCLK_I2C3 335 128 #define PCLK_I2C4 336 129 #define PCLK_I2C5 337 130 #define PCLK_SPI0 338 131 #define PCLK_SPI1 339 132 #define PCLK_SPI2 340 133 #define PCLK_UART0 341 134 #define PCLK_UART1 342 135 #define PCLK_UART2 343 136 #define PCLK_UART3 344 137 #define PCLK_UART4 345 138 #define PCLK_TSADC 346 139 #define PCLK_SARADC 347 140 #define PCLK_SIM 348 141 #define PCLK_GMAC 349 142 #define PCLK_PWM 350 143 #define PCLK_RKPWM 351 144 #define PCLK_PS2C 352 145 #define PCLK_TIMER 353 146 #define PCLK_TZPC 354 147 #define PCLK_EDP_CTRL 355 148 #define PCLK_MIPI_DSI0 356 149 #define PCLK_MIPI_DSI1 357 150 #define PCLK_MIPI_CSI 358 151 #define PCLK_LVDS_PHY 359 152 #define PCLK_HDMI_CTRL 360 153 #define PCLK_VIO2_H2P 361 154 #define PCLK_CPU 362 155 #define PCLK_PERI 363 156 #define PCLK_DDRUPCTL0 364 157 #define PCLK_PUBL0 365 158 #define PCLK_DDRUPCTL1 366 159 #define PCLK_PUBL1 367 160 #define PCLK_WDT 368 161 #define PCLK_EFUSE256 369 162 #define PCLK_EFUSE1024 370 163 #define PCLK_ISP_IN 371 164 165 /* hclk gates */ 166 #define HCLK_GPS 448 167 #define HCLK_OTG0 449 168 #define HCLK_USBHOST0 450 169 #define HCLK_USBHOST1 451 170 #define HCLK_HSIC 452 171 #define HCLK_NANDC0 453 172 #define HCLK_NANDC1 454 173 #define HCLK_TSP 455 174 #define HCLK_SDMMC 456 175 #define HCLK_SDIO0 457 176 #define HCLK_SDIO1 458 177 #define HCLK_EMMC 459 178 #define HCLK_HSADC 460 179 #define HCLK_CRYPTO 461 180 #define HCLK_I2S0 462 181 #define HCLK_SPDIF 463 182 #define HCLK_SPDIF8CH 464 183 #define HCLK_VOP0 465 184 #define HCLK_VOP1 466 185 #define HCLK_ROM 467 186 #define HCLK_IEP 468 187 #define HCLK_ISP 469 188 #define HCLK_RGA 470 189 #define HCLK_VIO_AHB_ARBI 471 190 #define HCLK_VIO_NIU 472 191 #define HCLK_VIP 473 192 #define HCLK_VIO2_H2P 474 193 #define HCLK_HEVC 475 194 #define HCLK_VCODEC 476 195 #define HCLK_CPU 477 196 #define HCLK_PERI 478 197 198 #define CLK_NR_CLKS (HCLK_PERI + 1 199 200 /* soft-reset indices */ 201 #define SRST_CORE0 0 202 #define SRST_CORE1 1 203 #define SRST_CORE2 2 204 #define SRST_CORE3 3 205 #define SRST_CORE0_PO 4 206 #define SRST_CORE1_PO 5 207 #define SRST_CORE2_PO 6 208 #define SRST_CORE3_PO 7 209 #define SRST_PDCORE_STRSYS 8 210 #define SRST_PDBUS_STRSYS 9 211 #define SRST_L2C 10 212 #define SRST_TOPDBG 11 213 #define SRST_CORE0_DBG 12 214 #define SRST_CORE1_DBG 13 215 #define SRST_CORE2_DBG 14 216 #define SRST_CORE3_DBG 15 217 218 #define SRST_PDBUG_AHB_ARBITOR 16 219 #define SRST_EFUSE256 17 220 #define SRST_DMAC1 18 221 #define SRST_INTMEM 19 222 #define SRST_ROM 20 223 #define SRST_SPDIF8CH 21 224 #define SRST_TIMER 22 225 #define SRST_I2S0 23 226 #define SRST_SPDIF 24 227 #define SRST_TIMER0 25 228 #define SRST_TIMER1 26 229 #define SRST_TIMER2 27 230 #define SRST_TIMER3 28 231 #define SRST_TIMER4 29 232 #define SRST_TIMER5 30 233 #define SRST_EFUSE 31 234 235 #define SRST_GPIO0 32 236 #define SRST_GPIO1 33 237 #define SRST_GPIO2 34 238 #define SRST_GPIO3 35 239 #define SRST_GPIO4 36 240 #define SRST_GPIO5 37 241 #define SRST_GPIO6 38 242 #define SRST_GPIO7 39 243 #define SRST_GPIO8 40 244 #define SRST_I2C0 42 245 #define SRST_I2C1 43 246 #define SRST_I2C2 44 247 #define SRST_I2C3 45 248 #define SRST_I2C4 46 249 #define SRST_I2C5 47 250 251 #define SRST_DWPWM 48 252 #define SRST_MMC_PERI 49 253 #define SRST_PERIPH_MMU 50 254 #define SRST_DAP 51 255 #define SRST_DAP_SYS 52 256 #define SRST_TPIU 53 257 #define SRST_PMU_APB 54 258 #define SRST_GRF 55 259 #define SRST_PMU 56 260 #define SRST_PERIPH_AXI 57 261 #define SRST_PERIPH_AHB 58 262 #define SRST_PERIPH_APB 59 263 #define SRST_PERIPH_NIU 60 264 #define SRST_PDPERI_AHB_ARBI 61 265 #define SRST_EMEM 62 266 #define SRST_USB_PERI 63 267 268 #define SRST_DMAC2 64 269 #define SRST_MAC 66 270 #define SRST_GPS 67 271 #define SRST_RKPWM 69 272 #define SRST_CCP 71 273 #define SRST_USBHOST0 72 274 #define SRST_HSIC 73 275 #define SRST_HSIC_AUX 74 276 #define SRST_HSIC_PHY 75 277 #define SRST_HSADC 76 278 #define SRST_NANDC0 77 279 #define SRST_NANDC1 78 280 281 #define SRST_TZPC 80 282 #define SRST_SPI0 83 283 #define SRST_SPI1 84 284 #define SRST_SPI2 85 285 #define SRST_SARADC 87 286 #define SRST_PDALIVE_NIU 88 287 #define SRST_PDPMU_INTMEM 89 288 #define SRST_PDPMU_NIU 90 289 #define SRST_SGRF 91 290 291 #define SRST_VIO_ARBI 96 292 #define SRST_RGA_NIU 97 293 #define SRST_VIO0_NIU_AXI 98 294 #define SRST_VIO_NIU_AHB 99 295 #define SRST_LCDC0_AXI 100 296 #define SRST_LCDC0_AHB 101 297 #define SRST_LCDC0_DCLK 102 298 #define SRST_VIO1_NIU_AXI 103 299 #define SRST_VIP 104 300 #define SRST_RGA_CORE 105 301 #define SRST_IEP_AXI 106 302 #define SRST_IEP_AHB 107 303 #define SRST_RGA_AXI 108 304 #define SRST_RGA_AHB 109 305 #define SRST_ISP 110 306 #define SRST_EDP 111 307 308 #define SRST_VCODEC_AXI 112 309 #define SRST_VCODEC_AHB 113 310 #define SRST_VIO_H2P 114 311 #define SRST_MIPIDSI0 115 312 #define SRST_MIPIDSI1 116 313 #define SRST_MIPICSI 117 314 #define SRST_LVDS_PHY 118 315 #define SRST_LVDS_CON 119 316 #define SRST_GPU 120 317 #define SRST_HDMI 121 318 #define SRST_CORE_PVTM 124 319 #define SRST_GPU_PVTM 125 320 321 #define SRST_MMC0 128 322 #define SRST_SDIO0 129 323 #define SRST_SDIO1 130 324 #define SRST_EMMC 131 325 #define SRST_USBOTG_AHB 132 326 #define SRST_USBOTG_PHY 133 327 #define SRST_USBOTG_CON 134 328 #define SRST_USBHOST0_AHB 135 329 #define SRST_USBHOST0_PHY 136 330 #define SRST_USBHOST0_CON 137 331 #define SRST_USBHOST1_AHB 138 332 #define SRST_USBHOST1_PHY 139 333 #define SRST_USBHOST1_CON 140 334 #define SRST_USB_ADP 141 335 #define SRST_ACC_EFUSE 142 336 337 #define SRST_CORESIGHT 144 338 #define SRST_PD_CORE_AHB_NOC 145 339 #define SRST_PD_CORE_APB_NOC 146 340 #define SRST_PD_CORE_MP_AXI 147 341 #define SRST_GIC 148 342 #define SRST_LCDC_PWM0 149 343 #define SRST_LCDC_PWM1 150 344 #define SRST_VIO0_H2P_BRG 151 345 #define SRST_VIO1_H2P_BRG 152 346 #define SRST_RGA_H2P_BRG 153 347 #define SRST_HEVC 154 348 #define SRST_TSADC 159 349 350 #define SRST_DDRPHY0 160 351 #define SRST_DDRPHY0_APB 161 352 #define SRST_DDRCTRL0 162 353 #define SRST_DDRCTRL0_APB 163 354 #define SRST_DDRPHY0_CTRL 164 355 #define SRST_DDRPHY1 165 356 #define SRST_DDRPHY1_APB 166 357 #define SRST_DDRCTRL1 167 358 #define SRST_DDRCTRL1_APB 168 359 #define SRST_DDRPHY1_CTRL 169 360 #define SRST_DDRMSCH0 170 361 #define SRST_DDRMSCH1 171 362 #define SRST_CRYPTO 174 363 #define SRST_C2C_HOST 175 364 365 #define SRST_LCDC1_AXI 176 366 #define SRST_LCDC1_AHB 177 367 #define SRST_LCDC1_DCLK 178 368 #define SRST_UART0 179 369 #define SRST_UART1 180 370 #define SRST_UART2 181 371 #define SRST_UART3 182 372 #define SRST_UART4 183 373 #define SRST_SIMC 186 374 #define SRST_PS2C 187 375 #define SRST_TSP 188 376 #define SRST_TSP_CLKIN0 189 377 #define SRST_TSP_CLKIN1 190 378 #define SRST_TSP_27M 191 379 380 #endif 381
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