1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms of the GNU General Public License as published by
>> 7 * the Free Software Foundation; either version 2 of the License, or
>> 8 * (at your option) any later version.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
5 */ 14 */
6 15
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
9 18
10 /* core clocks */ 19 /* core clocks */
11 #define PLL_APLL 1 20 #define PLL_APLL 1
12 #define PLL_DPLL 2 21 #define PLL_DPLL 2
13 #define PLL_CPLL 3 22 #define PLL_CPLL 3
14 #define PLL_GPLL 4 23 #define PLL_GPLL 4
15 #define PLL_NPLL 5 24 #define PLL_NPLL 5
16 #define ARMCLK 6 25 #define ARMCLK 6
17 26
18 /* sclk gates (special clocks) */ 27 /* sclk gates (special clocks) */
19 #define SCLK_GPU 64 28 #define SCLK_GPU 64
20 #define SCLK_SPI0 65 29 #define SCLK_SPI0 65
21 #define SCLK_SPI1 66 30 #define SCLK_SPI1 66
22 #define SCLK_SPI2 67 31 #define SCLK_SPI2 67
23 #define SCLK_SDMMC 68 32 #define SCLK_SDMMC 68
24 #define SCLK_SDIO0 69 33 #define SCLK_SDIO0 69
25 #define SCLK_SDIO1 70 34 #define SCLK_SDIO1 70
26 #define SCLK_EMMC 71 35 #define SCLK_EMMC 71
27 #define SCLK_TSADC 72 36 #define SCLK_TSADC 72
28 #define SCLK_SARADC 73 37 #define SCLK_SARADC 73
29 #define SCLK_PS2C 74 38 #define SCLK_PS2C 74
30 #define SCLK_NANDC0 75 39 #define SCLK_NANDC0 75
31 #define SCLK_NANDC1 76 40 #define SCLK_NANDC1 76
32 #define SCLK_UART0 77 41 #define SCLK_UART0 77
33 #define SCLK_UART1 78 42 #define SCLK_UART1 78
34 #define SCLK_UART2 79 43 #define SCLK_UART2 79
35 #define SCLK_UART3 80 44 #define SCLK_UART3 80
36 #define SCLK_UART4 81 45 #define SCLK_UART4 81
37 #define SCLK_I2S0 82 46 #define SCLK_I2S0 82
38 #define SCLK_SPDIF 83 47 #define SCLK_SPDIF 83
39 #define SCLK_SPDIF8CH 84 48 #define SCLK_SPDIF8CH 84
40 #define SCLK_TIMER0 85 49 #define SCLK_TIMER0 85
41 #define SCLK_TIMER1 86 50 #define SCLK_TIMER1 86
42 #define SCLK_TIMER2 87 51 #define SCLK_TIMER2 87
43 #define SCLK_TIMER3 88 52 #define SCLK_TIMER3 88
44 #define SCLK_TIMER4 89 53 #define SCLK_TIMER4 89
45 #define SCLK_TIMER5 90 54 #define SCLK_TIMER5 90
46 #define SCLK_TIMER6 91 55 #define SCLK_TIMER6 91
47 #define SCLK_HSADC 92 56 #define SCLK_HSADC 92
48 #define SCLK_OTGPHY0 93 57 #define SCLK_OTGPHY0 93
49 #define SCLK_OTGPHY1 94 58 #define SCLK_OTGPHY1 94
50 #define SCLK_OTGPHY2 95 59 #define SCLK_OTGPHY2 95
51 #define SCLK_OTG_ADP 96 60 #define SCLK_OTG_ADP 96
52 #define SCLK_HSICPHY480M 97 61 #define SCLK_HSICPHY480M 97
53 #define SCLK_HSICPHY12M 98 62 #define SCLK_HSICPHY12M 98
54 #define SCLK_MACREF 99 63 #define SCLK_MACREF 99
55 #define SCLK_LCDC_PWM0 100 64 #define SCLK_LCDC_PWM0 100
56 #define SCLK_LCDC_PWM1 101 65 #define SCLK_LCDC_PWM1 101
57 #define SCLK_MAC_RX 102 66 #define SCLK_MAC_RX 102
58 #define SCLK_MAC_TX 103 67 #define SCLK_MAC_TX 103
59 #define SCLK_EDP_24M 104 68 #define SCLK_EDP_24M 104
60 #define SCLK_EDP 105 69 #define SCLK_EDP 105
61 #define SCLK_RGA 106 70 #define SCLK_RGA 106
62 #define SCLK_ISP 107 71 #define SCLK_ISP 107
63 #define SCLK_ISP_JPE 108 72 #define SCLK_ISP_JPE 108
64 #define SCLK_HDMI_HDCP 109 73 #define SCLK_HDMI_HDCP 109
65 #define SCLK_HDMI_CEC 110 74 #define SCLK_HDMI_CEC 110
66 #define SCLK_HEVC_CABAC 111 75 #define SCLK_HEVC_CABAC 111
67 #define SCLK_HEVC_CORE 112 76 #define SCLK_HEVC_CORE 112
68 #define SCLK_I2S0_OUT 113 77 #define SCLK_I2S0_OUT 113
69 #define SCLK_SDMMC_DRV 114 78 #define SCLK_SDMMC_DRV 114
70 #define SCLK_SDIO0_DRV 115 79 #define SCLK_SDIO0_DRV 115
71 #define SCLK_SDIO1_DRV 116 80 #define SCLK_SDIO1_DRV 116
72 #define SCLK_EMMC_DRV 117 81 #define SCLK_EMMC_DRV 117
73 #define SCLK_SDMMC_SAMPLE 118 82 #define SCLK_SDMMC_SAMPLE 118
74 #define SCLK_SDIO0_SAMPLE 119 83 #define SCLK_SDIO0_SAMPLE 119
75 #define SCLK_SDIO1_SAMPLE 120 84 #define SCLK_SDIO1_SAMPLE 120
76 #define SCLK_EMMC_SAMPLE 121 85 #define SCLK_EMMC_SAMPLE 121
77 #define SCLK_USBPHY480M_SRC 122 86 #define SCLK_USBPHY480M_SRC 122
78 #define SCLK_PVTM_CORE 123 87 #define SCLK_PVTM_CORE 123
79 #define SCLK_PVTM_GPU 124 88 #define SCLK_PVTM_GPU 124
80 #define SCLK_CRYPTO 125 <<
81 #define SCLK_MIPIDSI_24M 126 <<
82 #define SCLK_VIP_OUT 127 <<
83 89
84 #define SCLK_MAC 151 90 #define SCLK_MAC 151
85 #define SCLK_MACREF_OUT 152 91 #define SCLK_MACREF_OUT 152
86 92
87 #define DCLK_VOP0 190 93 #define DCLK_VOP0 190
88 #define DCLK_VOP1 191 94 #define DCLK_VOP1 191
89 95
90 /* aclk gates */ 96 /* aclk gates */
91 #define ACLK_GPU 192 97 #define ACLK_GPU 192
92 #define ACLK_DMAC1 193 98 #define ACLK_DMAC1 193
93 #define ACLK_DMAC2 194 99 #define ACLK_DMAC2 194
94 #define ACLK_MMU 195 100 #define ACLK_MMU 195
95 #define ACLK_GMAC 196 101 #define ACLK_GMAC 196
96 #define ACLK_VOP0 197 102 #define ACLK_VOP0 197
97 #define ACLK_VOP1 198 103 #define ACLK_VOP1 198
98 #define ACLK_CRYPTO 199 104 #define ACLK_CRYPTO 199
99 #define ACLK_RGA 200 105 #define ACLK_RGA 200
100 #define ACLK_RGA_NIU 201 106 #define ACLK_RGA_NIU 201
101 #define ACLK_IEP 202 107 #define ACLK_IEP 202
102 #define ACLK_VIO0_NIU 203 108 #define ACLK_VIO0_NIU 203
103 #define ACLK_VIP 204 109 #define ACLK_VIP 204
104 #define ACLK_ISP 205 110 #define ACLK_ISP 205
105 #define ACLK_VIO1_NIU 206 111 #define ACLK_VIO1_NIU 206
106 #define ACLK_HEVC 207 112 #define ACLK_HEVC 207
107 #define ACLK_VCODEC 208 113 #define ACLK_VCODEC 208
108 #define ACLK_CPU 209 114 #define ACLK_CPU 209
109 #define ACLK_PERI 210 115 #define ACLK_PERI 210
110 116
111 /* pclk gates */ 117 /* pclk gates */
112 #define PCLK_GPIO0 320 118 #define PCLK_GPIO0 320
113 #define PCLK_GPIO1 321 119 #define PCLK_GPIO1 321
114 #define PCLK_GPIO2 322 120 #define PCLK_GPIO2 322
115 #define PCLK_GPIO3 323 121 #define PCLK_GPIO3 323
116 #define PCLK_GPIO4 324 122 #define PCLK_GPIO4 324
117 #define PCLK_GPIO5 325 123 #define PCLK_GPIO5 325
118 #define PCLK_GPIO6 326 124 #define PCLK_GPIO6 326
119 #define PCLK_GPIO7 327 125 #define PCLK_GPIO7 327
120 #define PCLK_GPIO8 328 126 #define PCLK_GPIO8 328
121 #define PCLK_GRF 329 127 #define PCLK_GRF 329
122 #define PCLK_SGRF 330 128 #define PCLK_SGRF 330
123 #define PCLK_PMU 331 129 #define PCLK_PMU 331
124 #define PCLK_I2C0 332 130 #define PCLK_I2C0 332
125 #define PCLK_I2C1 333 131 #define PCLK_I2C1 333
126 #define PCLK_I2C2 334 132 #define PCLK_I2C2 334
127 #define PCLK_I2C3 335 133 #define PCLK_I2C3 335
128 #define PCLK_I2C4 336 134 #define PCLK_I2C4 336
129 #define PCLK_I2C5 337 135 #define PCLK_I2C5 337
130 #define PCLK_SPI0 338 136 #define PCLK_SPI0 338
131 #define PCLK_SPI1 339 137 #define PCLK_SPI1 339
132 #define PCLK_SPI2 340 138 #define PCLK_SPI2 340
133 #define PCLK_UART0 341 139 #define PCLK_UART0 341
134 #define PCLK_UART1 342 140 #define PCLK_UART1 342
135 #define PCLK_UART2 343 141 #define PCLK_UART2 343
136 #define PCLK_UART3 344 142 #define PCLK_UART3 344
137 #define PCLK_UART4 345 143 #define PCLK_UART4 345
138 #define PCLK_TSADC 346 144 #define PCLK_TSADC 346
139 #define PCLK_SARADC 347 145 #define PCLK_SARADC 347
140 #define PCLK_SIM 348 146 #define PCLK_SIM 348
141 #define PCLK_GMAC 349 147 #define PCLK_GMAC 349
142 #define PCLK_PWM 350 148 #define PCLK_PWM 350
143 #define PCLK_RKPWM 351 149 #define PCLK_RKPWM 351
144 #define PCLK_PS2C 352 150 #define PCLK_PS2C 352
145 #define PCLK_TIMER 353 151 #define PCLK_TIMER 353
146 #define PCLK_TZPC 354 152 #define PCLK_TZPC 354
147 #define PCLK_EDP_CTRL 355 153 #define PCLK_EDP_CTRL 355
148 #define PCLK_MIPI_DSI0 356 154 #define PCLK_MIPI_DSI0 356
149 #define PCLK_MIPI_DSI1 357 155 #define PCLK_MIPI_DSI1 357
150 #define PCLK_MIPI_CSI 358 156 #define PCLK_MIPI_CSI 358
151 #define PCLK_LVDS_PHY 359 157 #define PCLK_LVDS_PHY 359
152 #define PCLK_HDMI_CTRL 360 158 #define PCLK_HDMI_CTRL 360
153 #define PCLK_VIO2_H2P 361 159 #define PCLK_VIO2_H2P 361
154 #define PCLK_CPU 362 160 #define PCLK_CPU 362
155 #define PCLK_PERI 363 161 #define PCLK_PERI 363
156 #define PCLK_DDRUPCTL0 364 162 #define PCLK_DDRUPCTL0 364
157 #define PCLK_PUBL0 365 163 #define PCLK_PUBL0 365
158 #define PCLK_DDRUPCTL1 366 164 #define PCLK_DDRUPCTL1 366
159 #define PCLK_PUBL1 367 165 #define PCLK_PUBL1 367
160 #define PCLK_WDT 368 166 #define PCLK_WDT 368
161 #define PCLK_EFUSE256 369 <<
162 #define PCLK_EFUSE1024 370 <<
163 #define PCLK_ISP_IN 371 <<
164 167
165 /* hclk gates */ 168 /* hclk gates */
166 #define HCLK_GPS 448 169 #define HCLK_GPS 448
167 #define HCLK_OTG0 449 170 #define HCLK_OTG0 449
168 #define HCLK_USBHOST0 450 171 #define HCLK_USBHOST0 450
169 #define HCLK_USBHOST1 451 172 #define HCLK_USBHOST1 451
170 #define HCLK_HSIC 452 173 #define HCLK_HSIC 452
171 #define HCLK_NANDC0 453 174 #define HCLK_NANDC0 453
172 #define HCLK_NANDC1 454 175 #define HCLK_NANDC1 454
173 #define HCLK_TSP 455 176 #define HCLK_TSP 455
174 #define HCLK_SDMMC 456 177 #define HCLK_SDMMC 456
175 #define HCLK_SDIO0 457 178 #define HCLK_SDIO0 457
176 #define HCLK_SDIO1 458 179 #define HCLK_SDIO1 458
177 #define HCLK_EMMC 459 180 #define HCLK_EMMC 459
178 #define HCLK_HSADC 460 181 #define HCLK_HSADC 460
179 #define HCLK_CRYPTO 461 182 #define HCLK_CRYPTO 461
180 #define HCLK_I2S0 462 183 #define HCLK_I2S0 462
181 #define HCLK_SPDIF 463 184 #define HCLK_SPDIF 463
182 #define HCLK_SPDIF8CH 464 185 #define HCLK_SPDIF8CH 464
183 #define HCLK_VOP0 465 186 #define HCLK_VOP0 465
184 #define HCLK_VOP1 466 187 #define HCLK_VOP1 466
185 #define HCLK_ROM 467 188 #define HCLK_ROM 467
186 #define HCLK_IEP 468 189 #define HCLK_IEP 468
187 #define HCLK_ISP 469 190 #define HCLK_ISP 469
188 #define HCLK_RGA 470 191 #define HCLK_RGA 470
189 #define HCLK_VIO_AHB_ARBI 471 192 #define HCLK_VIO_AHB_ARBI 471
190 #define HCLK_VIO_NIU 472 193 #define HCLK_VIO_NIU 472
191 #define HCLK_VIP 473 194 #define HCLK_VIP 473
192 #define HCLK_VIO2_H2P 474 195 #define HCLK_VIO2_H2P 474
193 #define HCLK_HEVC 475 196 #define HCLK_HEVC 475
194 #define HCLK_VCODEC 476 197 #define HCLK_VCODEC 476
195 #define HCLK_CPU 477 198 #define HCLK_CPU 477
196 #define HCLK_PERI 478 199 #define HCLK_PERI 478
>> 200
>> 201 #define CLK_NR_CLKS (HCLK_PERI + 1)
197 202
198 /* soft-reset indices */ 203 /* soft-reset indices */
199 #define SRST_CORE0 0 204 #define SRST_CORE0 0
200 #define SRST_CORE1 1 205 #define SRST_CORE1 1
201 #define SRST_CORE2 2 206 #define SRST_CORE2 2
202 #define SRST_CORE3 3 207 #define SRST_CORE3 3
203 #define SRST_CORE0_PO 4 208 #define SRST_CORE0_PO 4
204 #define SRST_CORE1_PO 5 209 #define SRST_CORE1_PO 5
205 #define SRST_CORE2_PO 6 210 #define SRST_CORE2_PO 6
206 #define SRST_CORE3_PO 7 211 #define SRST_CORE3_PO 7
207 #define SRST_PDCORE_STRSYS 8 212 #define SRST_PDCORE_STRSYS 8
208 #define SRST_PDBUS_STRSYS 9 213 #define SRST_PDBUS_STRSYS 9
209 #define SRST_L2C 10 214 #define SRST_L2C 10
210 #define SRST_TOPDBG 11 215 #define SRST_TOPDBG 11
211 #define SRST_CORE0_DBG 12 216 #define SRST_CORE0_DBG 12
212 #define SRST_CORE1_DBG 13 217 #define SRST_CORE1_DBG 13
213 #define SRST_CORE2_DBG 14 218 #define SRST_CORE2_DBG 14
214 #define SRST_CORE3_DBG 15 219 #define SRST_CORE3_DBG 15
215 220
216 #define SRST_PDBUG_AHB_ARBITOR 16 221 #define SRST_PDBUG_AHB_ARBITOR 16
217 #define SRST_EFUSE256 17 222 #define SRST_EFUSE256 17
218 #define SRST_DMAC1 18 223 #define SRST_DMAC1 18
219 #define SRST_INTMEM 19 224 #define SRST_INTMEM 19
220 #define SRST_ROM 20 225 #define SRST_ROM 20
221 #define SRST_SPDIF8CH 21 226 #define SRST_SPDIF8CH 21
222 #define SRST_TIMER 22 227 #define SRST_TIMER 22
223 #define SRST_I2S0 23 228 #define SRST_I2S0 23
224 #define SRST_SPDIF 24 229 #define SRST_SPDIF 24
225 #define SRST_TIMER0 25 230 #define SRST_TIMER0 25
226 #define SRST_TIMER1 26 231 #define SRST_TIMER1 26
227 #define SRST_TIMER2 27 232 #define SRST_TIMER2 27
228 #define SRST_TIMER3 28 233 #define SRST_TIMER3 28
229 #define SRST_TIMER4 29 234 #define SRST_TIMER4 29
230 #define SRST_TIMER5 30 235 #define SRST_TIMER5 30
231 #define SRST_EFUSE 31 236 #define SRST_EFUSE 31
232 237
233 #define SRST_GPIO0 32 238 #define SRST_GPIO0 32
234 #define SRST_GPIO1 33 239 #define SRST_GPIO1 33
235 #define SRST_GPIO2 34 240 #define SRST_GPIO2 34
236 #define SRST_GPIO3 35 241 #define SRST_GPIO3 35
237 #define SRST_GPIO4 36 242 #define SRST_GPIO4 36
238 #define SRST_GPIO5 37 243 #define SRST_GPIO5 37
239 #define SRST_GPIO6 38 244 #define SRST_GPIO6 38
240 #define SRST_GPIO7 39 245 #define SRST_GPIO7 39
241 #define SRST_GPIO8 40 246 #define SRST_GPIO8 40
242 #define SRST_I2C0 42 247 #define SRST_I2C0 42
243 #define SRST_I2C1 43 248 #define SRST_I2C1 43
244 #define SRST_I2C2 44 249 #define SRST_I2C2 44
245 #define SRST_I2C3 45 250 #define SRST_I2C3 45
246 #define SRST_I2C4 46 251 #define SRST_I2C4 46
247 #define SRST_I2C5 47 252 #define SRST_I2C5 47
248 253
249 #define SRST_DWPWM 48 254 #define SRST_DWPWM 48
250 #define SRST_MMC_PERI 49 255 #define SRST_MMC_PERI 49
251 #define SRST_PERIPH_MMU 50 256 #define SRST_PERIPH_MMU 50
252 #define SRST_DAP 51 257 #define SRST_DAP 51
253 #define SRST_DAP_SYS 52 258 #define SRST_DAP_SYS 52
254 #define SRST_TPIU 53 259 #define SRST_TPIU 53
255 #define SRST_PMU_APB 54 260 #define SRST_PMU_APB 54
256 #define SRST_GRF 55 261 #define SRST_GRF 55
257 #define SRST_PMU 56 262 #define SRST_PMU 56
258 #define SRST_PERIPH_AXI 57 263 #define SRST_PERIPH_AXI 57
259 #define SRST_PERIPH_AHB 58 264 #define SRST_PERIPH_AHB 58
260 #define SRST_PERIPH_APB 59 265 #define SRST_PERIPH_APB 59
261 #define SRST_PERIPH_NIU 60 266 #define SRST_PERIPH_NIU 60
262 #define SRST_PDPERI_AHB_ARBI 61 267 #define SRST_PDPERI_AHB_ARBI 61
263 #define SRST_EMEM 62 268 #define SRST_EMEM 62
264 #define SRST_USB_PERI 63 269 #define SRST_USB_PERI 63
265 270
266 #define SRST_DMAC2 64 271 #define SRST_DMAC2 64
267 #define SRST_MAC 66 272 #define SRST_MAC 66
268 #define SRST_GPS 67 273 #define SRST_GPS 67
269 #define SRST_RKPWM 69 274 #define SRST_RKPWM 69
270 #define SRST_CCP 71 275 #define SRST_CCP 71
271 #define SRST_USBHOST0 72 276 #define SRST_USBHOST0 72
272 #define SRST_HSIC 73 277 #define SRST_HSIC 73
273 #define SRST_HSIC_AUX 74 278 #define SRST_HSIC_AUX 74
274 #define SRST_HSIC_PHY 75 279 #define SRST_HSIC_PHY 75
275 #define SRST_HSADC 76 280 #define SRST_HSADC 76
276 #define SRST_NANDC0 77 281 #define SRST_NANDC0 77
277 #define SRST_NANDC1 78 282 #define SRST_NANDC1 78
278 283
279 #define SRST_TZPC 80 284 #define SRST_TZPC 80
280 #define SRST_SPI0 83 285 #define SRST_SPI0 83
281 #define SRST_SPI1 84 286 #define SRST_SPI1 84
282 #define SRST_SPI2 85 287 #define SRST_SPI2 85
283 #define SRST_SARADC 87 288 #define SRST_SARADC 87
284 #define SRST_PDALIVE_NIU 88 289 #define SRST_PDALIVE_NIU 88
285 #define SRST_PDPMU_INTMEM 89 290 #define SRST_PDPMU_INTMEM 89
286 #define SRST_PDPMU_NIU 90 291 #define SRST_PDPMU_NIU 90
287 #define SRST_SGRF 91 292 #define SRST_SGRF 91
288 293
289 #define SRST_VIO_ARBI 96 294 #define SRST_VIO_ARBI 96
290 #define SRST_RGA_NIU 97 295 #define SRST_RGA_NIU 97
291 #define SRST_VIO0_NIU_AXI 98 296 #define SRST_VIO0_NIU_AXI 98
292 #define SRST_VIO_NIU_AHB 99 297 #define SRST_VIO_NIU_AHB 99
293 #define SRST_LCDC0_AXI 100 298 #define SRST_LCDC0_AXI 100
294 #define SRST_LCDC0_AHB 101 299 #define SRST_LCDC0_AHB 101
295 #define SRST_LCDC0_DCLK 102 300 #define SRST_LCDC0_DCLK 102
296 #define SRST_VIO1_NIU_AXI 103 301 #define SRST_VIO1_NIU_AXI 103
297 #define SRST_VIP 104 302 #define SRST_VIP 104
298 #define SRST_RGA_CORE 105 303 #define SRST_RGA_CORE 105
299 #define SRST_IEP_AXI 106 304 #define SRST_IEP_AXI 106
300 #define SRST_IEP_AHB 107 305 #define SRST_IEP_AHB 107
301 #define SRST_RGA_AXI 108 306 #define SRST_RGA_AXI 108
302 #define SRST_RGA_AHB 109 307 #define SRST_RGA_AHB 109
303 #define SRST_ISP 110 308 #define SRST_ISP 110
304 #define SRST_EDP 111 309 #define SRST_EDP 111
305 310
306 #define SRST_VCODEC_AXI 112 311 #define SRST_VCODEC_AXI 112
307 #define SRST_VCODEC_AHB 113 312 #define SRST_VCODEC_AHB 113
308 #define SRST_VIO_H2P 114 313 #define SRST_VIO_H2P 114
309 #define SRST_MIPIDSI0 115 314 #define SRST_MIPIDSI0 115
310 #define SRST_MIPIDSI1 116 315 #define SRST_MIPIDSI1 116
311 #define SRST_MIPICSI 117 316 #define SRST_MIPICSI 117
312 #define SRST_LVDS_PHY 118 317 #define SRST_LVDS_PHY 118
313 #define SRST_LVDS_CON 119 318 #define SRST_LVDS_CON 119
314 #define SRST_GPU 120 319 #define SRST_GPU 120
315 #define SRST_HDMI 121 320 #define SRST_HDMI 121
316 #define SRST_CORE_PVTM 124 321 #define SRST_CORE_PVTM 124
317 #define SRST_GPU_PVTM 125 322 #define SRST_GPU_PVTM 125
318 323
319 #define SRST_MMC0 128 324 #define SRST_MMC0 128
320 #define SRST_SDIO0 129 325 #define SRST_SDIO0 129
321 #define SRST_SDIO1 130 326 #define SRST_SDIO1 130
322 #define SRST_EMMC 131 327 #define SRST_EMMC 131
323 #define SRST_USBOTG_AHB 132 328 #define SRST_USBOTG_AHB 132
324 #define SRST_USBOTG_PHY 133 329 #define SRST_USBOTG_PHY 133
325 #define SRST_USBOTG_CON 134 330 #define SRST_USBOTG_CON 134
326 #define SRST_USBHOST0_AHB 135 331 #define SRST_USBHOST0_AHB 135
327 #define SRST_USBHOST0_PHY 136 332 #define SRST_USBHOST0_PHY 136
328 #define SRST_USBHOST0_CON 137 333 #define SRST_USBHOST0_CON 137
329 #define SRST_USBHOST1_AHB 138 334 #define SRST_USBHOST1_AHB 138
330 #define SRST_USBHOST1_PHY 139 335 #define SRST_USBHOST1_PHY 139
331 #define SRST_USBHOST1_CON 140 336 #define SRST_USBHOST1_CON 140
332 #define SRST_USB_ADP 141 337 #define SRST_USB_ADP 141
333 #define SRST_ACC_EFUSE 142 338 #define SRST_ACC_EFUSE 142
334 339
335 #define SRST_CORESIGHT 144 340 #define SRST_CORESIGHT 144
336 #define SRST_PD_CORE_AHB_NOC 145 341 #define SRST_PD_CORE_AHB_NOC 145
337 #define SRST_PD_CORE_APB_NOC 146 342 #define SRST_PD_CORE_APB_NOC 146
338 #define SRST_PD_CORE_MP_AXI 147 343 #define SRST_PD_CORE_MP_AXI 147
339 #define SRST_GIC 148 344 #define SRST_GIC 148
340 #define SRST_LCDC_PWM0 149 345 #define SRST_LCDC_PWM0 149
341 #define SRST_LCDC_PWM1 150 346 #define SRST_LCDC_PWM1 150
342 #define SRST_VIO0_H2P_BRG 151 347 #define SRST_VIO0_H2P_BRG 151
343 #define SRST_VIO1_H2P_BRG 152 348 #define SRST_VIO1_H2P_BRG 152
344 #define SRST_RGA_H2P_BRG 153 349 #define SRST_RGA_H2P_BRG 153
345 #define SRST_HEVC 154 350 #define SRST_HEVC 154
346 #define SRST_TSADC 159 351 #define SRST_TSADC 159
347 352
348 #define SRST_DDRPHY0 160 353 #define SRST_DDRPHY0 160
349 #define SRST_DDRPHY0_APB 161 354 #define SRST_DDRPHY0_APB 161
350 #define SRST_DDRCTRL0 162 355 #define SRST_DDRCTRL0 162
351 #define SRST_DDRCTRL0_APB 163 356 #define SRST_DDRCTRL0_APB 163
352 #define SRST_DDRPHY0_CTRL 164 357 #define SRST_DDRPHY0_CTRL 164
353 #define SRST_DDRPHY1 165 358 #define SRST_DDRPHY1 165
354 #define SRST_DDRPHY1_APB 166 359 #define SRST_DDRPHY1_APB 166
355 #define SRST_DDRCTRL1 167 360 #define SRST_DDRCTRL1 167
356 #define SRST_DDRCTRL1_APB 168 361 #define SRST_DDRCTRL1_APB 168
357 #define SRST_DDRPHY1_CTRL 169 362 #define SRST_DDRPHY1_CTRL 169
358 #define SRST_DDRMSCH0 170 363 #define SRST_DDRMSCH0 170
359 #define SRST_DDRMSCH1 171 364 #define SRST_DDRMSCH1 171
360 #define SRST_CRYPTO 174 365 #define SRST_CRYPTO 174
361 #define SRST_C2C_HOST 175 366 #define SRST_C2C_HOST 175
362 367
363 #define SRST_LCDC1_AXI 176 368 #define SRST_LCDC1_AXI 176
364 #define SRST_LCDC1_AHB 177 369 #define SRST_LCDC1_AHB 177
365 #define SRST_LCDC1_DCLK 178 370 #define SRST_LCDC1_DCLK 178
366 #define SRST_UART0 179 371 #define SRST_UART0 179
367 #define SRST_UART1 180 372 #define SRST_UART1 180
368 #define SRST_UART2 181 373 #define SRST_UART2 181
369 #define SRST_UART3 182 374 #define SRST_UART3 182
370 #define SRST_UART4 183 375 #define SRST_UART4 183
371 #define SRST_SIMC 186 376 #define SRST_SIMC 186
372 #define SRST_PS2C 187 377 #define SRST_PS2C 187
373 #define SRST_TSP 188 378 #define SRST_TSP 188
374 #define SRST_TSP_CLKIN0 189 379 #define SRST_TSP_CLKIN0 189
375 #define SRST_TSP_CLKIN1 190 380 #define SRST_TSP_CLKIN1 190
376 #define SRST_TSP_27M 191 381 #define SRST_TSP_27M 191
377 382
378 #endif 383 #endif
379 384
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