1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sn 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License as published by
>> 6 * the Free Software Foundation; either version 2 of the License, or
>> 7 * (at your option) any later version.
>> 8 *
>> 9 * This program is distributed in the hope that it will be useful,
>> 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 12 * GNU General Public License for more details.
4 */ 13 */
5 14
6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 15 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 16 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
8 17
9 /* core clocks */ 18 /* core clocks */
10 #define PLL_APLLB 1 19 #define PLL_APLLB 1
11 #define PLL_APLLL 2 20 #define PLL_APLLL 2
12 #define PLL_DPLL 3 21 #define PLL_DPLL 3
13 #define PLL_CPLL 4 22 #define PLL_CPLL 4
14 #define PLL_GPLL 5 23 #define PLL_GPLL 5
15 #define PLL_NPLL 6 24 #define PLL_NPLL 6
16 #define ARMCLKB 7 25 #define ARMCLKB 7
17 #define ARMCLKL 8 26 #define ARMCLKL 8
18 27
19 /* sclk gates (special clocks) */ 28 /* sclk gates (special clocks) */
20 #define SCLK_GPU_CORE 64 29 #define SCLK_GPU_CORE 64
21 #define SCLK_SPI0 65 30 #define SCLK_SPI0 65
22 #define SCLK_SPI1 66 31 #define SCLK_SPI1 66
23 #define SCLK_SPI2 67 32 #define SCLK_SPI2 67
24 #define SCLK_SDMMC 68 33 #define SCLK_SDMMC 68
25 #define SCLK_SDIO0 69 34 #define SCLK_SDIO0 69
26 #define SCLK_EMMC 71 35 #define SCLK_EMMC 71
27 #define SCLK_TSADC 72 36 #define SCLK_TSADC 72
28 #define SCLK_SARADC 73 37 #define SCLK_SARADC 73
29 #define SCLK_NANDC0 75 38 #define SCLK_NANDC0 75
30 #define SCLK_UART0 77 39 #define SCLK_UART0 77
31 #define SCLK_UART1 78 40 #define SCLK_UART1 78
32 #define SCLK_UART2 79 41 #define SCLK_UART2 79
33 #define SCLK_UART3 80 42 #define SCLK_UART3 80
34 #define SCLK_UART4 81 43 #define SCLK_UART4 81
35 #define SCLK_I2S_8CH 82 44 #define SCLK_I2S_8CH 82
36 #define SCLK_SPDIF_8CH 83 45 #define SCLK_SPDIF_8CH 83
37 #define SCLK_I2S_2CH 84 46 #define SCLK_I2S_2CH 84
38 #define SCLK_TIMER00 85 !! 47 #define SCLK_TIMER0 85
39 #define SCLK_TIMER01 86 !! 48 #define SCLK_TIMER1 86
40 #define SCLK_TIMER02 87 !! 49 #define SCLK_TIMER2 87
41 #define SCLK_TIMER03 88 !! 50 #define SCLK_TIMER3 88
42 #define SCLK_TIMER04 89 !! 51 #define SCLK_TIMER4 89
43 #define SCLK_TIMER05 90 !! 52 #define SCLK_TIMER5 90
>> 53 #define SCLK_TIMER6 91
44 #define SCLK_OTGPHY0 93 54 #define SCLK_OTGPHY0 93
45 #define SCLK_OTG_ADP 96 55 #define SCLK_OTG_ADP 96
46 #define SCLK_HSICPHY480M 97 56 #define SCLK_HSICPHY480M 97
47 #define SCLK_HSICPHY12M 98 57 #define SCLK_HSICPHY12M 98
48 #define SCLK_MACREF 99 58 #define SCLK_MACREF 99
49 #define SCLK_VOP0_PWM 100 59 #define SCLK_VOP0_PWM 100
50 #define SCLK_MAC_RX 102 60 #define SCLK_MAC_RX 102
51 #define SCLK_MAC_TX 103 61 #define SCLK_MAC_TX 103
52 #define SCLK_EDP_24M 104 62 #define SCLK_EDP_24M 104
53 #define SCLK_EDP 105 63 #define SCLK_EDP 105
54 #define SCLK_RGA 106 64 #define SCLK_RGA 106
55 #define SCLK_ISP 107 65 #define SCLK_ISP 107
56 #define SCLK_HDCP 108 66 #define SCLK_HDCP 108
57 #define SCLK_HDMI_HDCP 109 67 #define SCLK_HDMI_HDCP 109
58 #define SCLK_HDMI_CEC 110 68 #define SCLK_HDMI_CEC 110
59 #define SCLK_HEVC_CABAC 111 69 #define SCLK_HEVC_CABAC 111
60 #define SCLK_HEVC_CORE 112 70 #define SCLK_HEVC_CORE 112
61 #define SCLK_I2S_8CH_OUT 113 71 #define SCLK_I2S_8CH_OUT 113
62 #define SCLK_SDMMC_DRV 114 72 #define SCLK_SDMMC_DRV 114
63 #define SCLK_SDIO0_DRV 115 73 #define SCLK_SDIO0_DRV 115
64 #define SCLK_EMMC_DRV 117 74 #define SCLK_EMMC_DRV 117
65 #define SCLK_SDMMC_SAMPLE 118 75 #define SCLK_SDMMC_SAMPLE 118
66 #define SCLK_SDIO0_SAMPLE 119 76 #define SCLK_SDIO0_SAMPLE 119
67 #define SCLK_EMMC_SAMPLE 121 77 #define SCLK_EMMC_SAMPLE 121
68 #define SCLK_USBPHY480M 122 78 #define SCLK_USBPHY480M 122
69 #define SCLK_PVTM_CORE 123 79 #define SCLK_PVTM_CORE 123
70 #define SCLK_PVTM_GPU 124 80 #define SCLK_PVTM_GPU 124
71 #define SCLK_PVTM_PMU 125 81 #define SCLK_PVTM_PMU 125
72 #define SCLK_SFC 126 82 #define SCLK_SFC 126
73 #define SCLK_MAC 127 83 #define SCLK_MAC 127
74 #define SCLK_MACREF_OUT 128 84 #define SCLK_MACREF_OUT 128
75 #define SCLK_TIMER10 133 <<
76 #define SCLK_TIMER11 134 <<
77 #define SCLK_TIMER12 135 <<
78 #define SCLK_TIMER13 136 <<
79 #define SCLK_TIMER14 137 <<
80 #define SCLK_TIMER15 138 <<
81 #define SCLK_VIP_OUT 139 <<
82 85
83 #define DCLK_VOP 190 86 #define DCLK_VOP 190
84 #define MCLK_CRYPTO 191 87 #define MCLK_CRYPTO 191
85 88
86 /* aclk gates */ 89 /* aclk gates */
87 #define ACLK_GPU_MEM 192 90 #define ACLK_GPU_MEM 192
88 #define ACLK_GPU_CFG 193 91 #define ACLK_GPU_CFG 193
89 #define ACLK_DMAC_BUS 194 92 #define ACLK_DMAC_BUS 194
90 #define ACLK_DMAC_PERI 195 93 #define ACLK_DMAC_PERI 195
91 #define ACLK_PERI_MMU 196 94 #define ACLK_PERI_MMU 196
92 #define ACLK_GMAC 197 95 #define ACLK_GMAC 197
93 #define ACLK_VOP 198 96 #define ACLK_VOP 198
94 #define ACLK_VOP_IEP 199 97 #define ACLK_VOP_IEP 199
95 #define ACLK_RGA 200 98 #define ACLK_RGA 200
96 #define ACLK_HDCP 201 99 #define ACLK_HDCP 201
97 #define ACLK_IEP 202 100 #define ACLK_IEP 202
98 #define ACLK_VIO0_NOC 203 101 #define ACLK_VIO0_NOC 203
99 #define ACLK_VIP 204 102 #define ACLK_VIP 204
100 #define ACLK_ISP 205 103 #define ACLK_ISP 205
101 #define ACLK_VIO1_NOC 206 104 #define ACLK_VIO1_NOC 206
102 #define ACLK_VIDEO 208 105 #define ACLK_VIDEO 208
103 #define ACLK_BUS 209 106 #define ACLK_BUS 209
104 #define ACLK_PERI 210 107 #define ACLK_PERI 210
105 108
106 /* pclk gates */ 109 /* pclk gates */
107 #define PCLK_GPIO0 320 110 #define PCLK_GPIO0 320
108 #define PCLK_GPIO1 321 111 #define PCLK_GPIO1 321
109 #define PCLK_GPIO2 322 112 #define PCLK_GPIO2 322
110 #define PCLK_GPIO3 323 113 #define PCLK_GPIO3 323
111 #define PCLK_PMUGRF 324 114 #define PCLK_PMUGRF 324
112 #define PCLK_MAILBOX 325 115 #define PCLK_MAILBOX 325
113 #define PCLK_GRF 329 116 #define PCLK_GRF 329
114 #define PCLK_SGRF 330 117 #define PCLK_SGRF 330
115 #define PCLK_PMU 331 118 #define PCLK_PMU 331
116 #define PCLK_I2C0 332 119 #define PCLK_I2C0 332
117 #define PCLK_I2C1 333 120 #define PCLK_I2C1 333
118 #define PCLK_I2C2 334 121 #define PCLK_I2C2 334
119 #define PCLK_I2C3 335 122 #define PCLK_I2C3 335
120 #define PCLK_I2C4 336 123 #define PCLK_I2C4 336
121 #define PCLK_I2C5 337 124 #define PCLK_I2C5 337
122 #define PCLK_SPI0 338 125 #define PCLK_SPI0 338
123 #define PCLK_SPI1 339 126 #define PCLK_SPI1 339
124 #define PCLK_SPI2 340 127 #define PCLK_SPI2 340
125 #define PCLK_UART0 341 128 #define PCLK_UART0 341
126 #define PCLK_UART1 342 129 #define PCLK_UART1 342
127 #define PCLK_UART2 343 130 #define PCLK_UART2 343
128 #define PCLK_UART3 344 131 #define PCLK_UART3 344
129 #define PCLK_UART4 345 132 #define PCLK_UART4 345
130 #define PCLK_TSADC 346 133 #define PCLK_TSADC 346
131 #define PCLK_SARADC 347 134 #define PCLK_SARADC 347
132 #define PCLK_SIM 348 135 #define PCLK_SIM 348
133 #define PCLK_GMAC 349 136 #define PCLK_GMAC 349
134 #define PCLK_PWM0 350 137 #define PCLK_PWM0 350
135 #define PCLK_PWM1 351 138 #define PCLK_PWM1 351
136 #define PCLK_TIMER0 353 139 #define PCLK_TIMER0 353
137 #define PCLK_TIMER1 354 140 #define PCLK_TIMER1 354
138 #define PCLK_EDP_CTRL 355 141 #define PCLK_EDP_CTRL 355
139 #define PCLK_MIPI_DSI0 356 142 #define PCLK_MIPI_DSI0 356
140 #define PCLK_MIPI_CSI 358 143 #define PCLK_MIPI_CSI 358
141 #define PCLK_HDCP 359 144 #define PCLK_HDCP 359
142 #define PCLK_HDMI_CTRL 360 145 #define PCLK_HDMI_CTRL 360
143 #define PCLK_VIO_H2P 361 146 #define PCLK_VIO_H2P 361
144 #define PCLK_BUS 362 147 #define PCLK_BUS 362
145 #define PCLK_PERI 363 148 #define PCLK_PERI 363
146 #define PCLK_DDRUPCTL 364 149 #define PCLK_DDRUPCTL 364
147 #define PCLK_DDRPHY 365 150 #define PCLK_DDRPHY 365
148 #define PCLK_ISP 366 151 #define PCLK_ISP 366
149 #define PCLK_VIP 367 152 #define PCLK_VIP 367
150 #define PCLK_WDT 368 153 #define PCLK_WDT 368
151 #define PCLK_EFUSE256 369 <<
152 #define PCLK_DPHYRX 370 <<
153 #define PCLK_DPHYTX0 371 <<
154 154
155 /* hclk gates */ 155 /* hclk gates */
156 #define HCLK_SFC 448 156 #define HCLK_SFC 448
157 #define HCLK_OTG0 449 157 #define HCLK_OTG0 449
158 #define HCLK_HOST0 450 158 #define HCLK_HOST0 450
159 #define HCLK_HOST1 451 159 #define HCLK_HOST1 451
160 #define HCLK_HSIC 452 160 #define HCLK_HSIC 452
161 #define HCLK_NANDC0 453 161 #define HCLK_NANDC0 453
162 #define HCLK_TSP 455 162 #define HCLK_TSP 455
163 #define HCLK_SDMMC 456 163 #define HCLK_SDMMC 456
164 #define HCLK_SDIO0 457 164 #define HCLK_SDIO0 457
165 #define HCLK_EMMC 459 165 #define HCLK_EMMC 459
166 #define HCLK_HSADC 460 166 #define HCLK_HSADC 460
167 #define HCLK_CRYPTO 461 167 #define HCLK_CRYPTO 461
168 #define HCLK_I2S_2CH 462 168 #define HCLK_I2S_2CH 462
169 #define HCLK_I2S_8CH 463 169 #define HCLK_I2S_8CH 463
170 #define HCLK_SPDIF 464 170 #define HCLK_SPDIF 464
171 #define HCLK_VOP 465 171 #define HCLK_VOP 465
172 #define HCLK_ROM 467 172 #define HCLK_ROM 467
173 #define HCLK_IEP 468 173 #define HCLK_IEP 468
174 #define HCLK_ISP 469 174 #define HCLK_ISP 469
175 #define HCLK_RGA 470 175 #define HCLK_RGA 470
176 #define HCLK_VIO_AHB_ARBI 471 176 #define HCLK_VIO_AHB_ARBI 471
177 #define HCLK_VIO_NOC 472 177 #define HCLK_VIO_NOC 472
178 #define HCLK_VIP 473 178 #define HCLK_VIP 473
179 #define HCLK_VIO_H2P 474 179 #define HCLK_VIO_H2P 474
180 #define HCLK_VIO_HDCPMMU 475 180 #define HCLK_VIO_HDCPMMU 475
181 #define HCLK_VIDEO 476 181 #define HCLK_VIDEO 476
182 #define HCLK_BUS 477 182 #define HCLK_BUS 477
183 #define HCLK_PERI 478 183 #define HCLK_PERI 478
184 184
185 #define CLK_NR_CLKS (HCLK_PERI + 1 185 #define CLK_NR_CLKS (HCLK_PERI + 1)
186 186
187 /* soft-reset indices */ 187 /* soft-reset indices */
188 #define SRST_CORE_B0 0 188 #define SRST_CORE_B0 0
189 #define SRST_CORE_B1 1 189 #define SRST_CORE_B1 1
190 #define SRST_CORE_B2 2 190 #define SRST_CORE_B2 2
191 #define SRST_CORE_B3 3 191 #define SRST_CORE_B3 3
192 #define SRST_CORE_B0_PO 4 192 #define SRST_CORE_B0_PO 4
193 #define SRST_CORE_B1_PO 5 193 #define SRST_CORE_B1_PO 5
194 #define SRST_CORE_B2_PO 6 194 #define SRST_CORE_B2_PO 6
195 #define SRST_CORE_B3_PO 7 195 #define SRST_CORE_B3_PO 7
196 #define SRST_L2_B 8 196 #define SRST_L2_B 8
197 #define SRST_ADB_B 9 197 #define SRST_ADB_B 9
198 #define SRST_PD_CORE_B_NIU 10 198 #define SRST_PD_CORE_B_NIU 10
199 #define SRST_PDBUS_STRSYS 11 199 #define SRST_PDBUS_STRSYS 11
200 #define SRST_SOCDBG_B 14 200 #define SRST_SOCDBG_B 14
201 #define SRST_CORE_B_DBG 15 201 #define SRST_CORE_B_DBG 15
202 202
203 #define SRST_DMAC1 18 203 #define SRST_DMAC1 18
204 #define SRST_INTMEM 19 204 #define SRST_INTMEM 19
205 #define SRST_ROM 20 205 #define SRST_ROM 20
206 #define SRST_SPDIF8CH 21 206 #define SRST_SPDIF8CH 21
207 #define SRST_I2S8CH 23 207 #define SRST_I2S8CH 23
208 #define SRST_MAILBOX 24 208 #define SRST_MAILBOX 24
209 #define SRST_I2S2CH 25 209 #define SRST_I2S2CH 25
210 #define SRST_EFUSE_256 26 210 #define SRST_EFUSE_256 26
211 #define SRST_MCU_SYS 28 211 #define SRST_MCU_SYS 28
212 #define SRST_MCU_PO 29 212 #define SRST_MCU_PO 29
213 #define SRST_MCU_NOC 30 213 #define SRST_MCU_NOC 30
214 #define SRST_EFUSE 31 214 #define SRST_EFUSE 31
215 215
216 #define SRST_GPIO0 32 216 #define SRST_GPIO0 32
217 #define SRST_GPIO1 33 217 #define SRST_GPIO1 33
218 #define SRST_GPIO2 34 218 #define SRST_GPIO2 34
219 #define SRST_GPIO3 35 219 #define SRST_GPIO3 35
220 #define SRST_GPIO4 36 220 #define SRST_GPIO4 36
221 #define SRST_PMUGRF 41 221 #define SRST_PMUGRF 41
222 #define SRST_I2C0 42 222 #define SRST_I2C0 42
223 #define SRST_I2C1 43 223 #define SRST_I2C1 43
224 #define SRST_I2C2 44 224 #define SRST_I2C2 44
225 #define SRST_I2C3 45 225 #define SRST_I2C3 45
226 #define SRST_I2C4 46 226 #define SRST_I2C4 46
227 #define SRST_I2C5 47 227 #define SRST_I2C5 47
228 228
229 #define SRST_DWPWM 48 229 #define SRST_DWPWM 48
230 #define SRST_MMC_PERI 49 230 #define SRST_MMC_PERI 49
231 #define SRST_PERIPH_MMU 50 231 #define SRST_PERIPH_MMU 50
232 #define SRST_GRF 55 232 #define SRST_GRF 55
233 #define SRST_PMU 56 233 #define SRST_PMU 56
234 #define SRST_PERIPH_AXI 57 234 #define SRST_PERIPH_AXI 57
235 #define SRST_PERIPH_AHB 58 235 #define SRST_PERIPH_AHB 58
236 #define SRST_PERIPH_APB 59 236 #define SRST_PERIPH_APB 59
237 #define SRST_PERIPH_NIU 60 237 #define SRST_PERIPH_NIU 60
238 #define SRST_PDPERI_AHB_ARBI 61 238 #define SRST_PDPERI_AHB_ARBI 61
239 #define SRST_EMEM 62 239 #define SRST_EMEM 62
240 #define SRST_USB_PERI 63 240 #define SRST_USB_PERI 63
241 241
242 #define SRST_DMAC2 64 242 #define SRST_DMAC2 64
243 #define SRST_MAC 66 243 #define SRST_MAC 66
244 #define SRST_GPS 67 244 #define SRST_GPS 67
245 #define SRST_RKPWM 69 245 #define SRST_RKPWM 69
246 #define SRST_USBHOST0 72 246 #define SRST_USBHOST0 72
247 #define SRST_HSIC 73 247 #define SRST_HSIC 73
248 #define SRST_HSIC_AUX 74 248 #define SRST_HSIC_AUX 74
249 #define SRST_HSIC_PHY 75 249 #define SRST_HSIC_PHY 75
250 #define SRST_HSADC 76 250 #define SRST_HSADC 76
251 #define SRST_NANDC0 77 251 #define SRST_NANDC0 77
252 #define SRST_SFC 79 252 #define SRST_SFC 79
253 253
254 #define SRST_SPI0 83 254 #define SRST_SPI0 83
255 #define SRST_SPI1 84 255 #define SRST_SPI1 84
256 #define SRST_SPI2 85 256 #define SRST_SPI2 85
257 #define SRST_SARADC 87 257 #define SRST_SARADC 87
258 #define SRST_PDALIVE_NIU 88 258 #define SRST_PDALIVE_NIU 88
259 #define SRST_PDPMU_INTMEM 89 259 #define SRST_PDPMU_INTMEM 89
260 #define SRST_PDPMU_NIU 90 260 #define SRST_PDPMU_NIU 90
261 #define SRST_SGRF 91 261 #define SRST_SGRF 91
262 262
263 #define SRST_VIO_ARBI 96 263 #define SRST_VIO_ARBI 96
264 #define SRST_RGA_NIU 97 264 #define SRST_RGA_NIU 97
265 #define SRST_VIO0_NIU_AXI 98 265 #define SRST_VIO0_NIU_AXI 98
266 #define SRST_VIO_NIU_AHB 99 266 #define SRST_VIO_NIU_AHB 99
267 #define SRST_LCDC0_AXI 100 267 #define SRST_LCDC0_AXI 100
268 #define SRST_LCDC0_AHB 101 268 #define SRST_LCDC0_AHB 101
269 #define SRST_LCDC0_DCLK 102 269 #define SRST_LCDC0_DCLK 102
270 #define SRST_VIP 104 270 #define SRST_VIP 104
271 #define SRST_RGA_CORE 105 271 #define SRST_RGA_CORE 105
272 #define SRST_IEP_AXI 106 272 #define SRST_IEP_AXI 106
273 #define SRST_IEP_AHB 107 273 #define SRST_IEP_AHB 107
274 #define SRST_RGA_AXI 108 274 #define SRST_RGA_AXI 108
275 #define SRST_RGA_AHB 109 275 #define SRST_RGA_AHB 109
276 #define SRST_ISP 110 276 #define SRST_ISP 110
277 #define SRST_EDP_24M 111 277 #define SRST_EDP_24M 111
278 278
279 #define SRST_VIDEO_AXI 112 279 #define SRST_VIDEO_AXI 112
280 #define SRST_VIDEO_AHB 113 280 #define SRST_VIDEO_AHB 113
281 #define SRST_MIPIDPHYTX 114 281 #define SRST_MIPIDPHYTX 114
282 #define SRST_MIPIDSI0 115 282 #define SRST_MIPIDSI0 115
283 #define SRST_MIPIDPHYRX 116 283 #define SRST_MIPIDPHYRX 116
284 #define SRST_MIPICSI 117 284 #define SRST_MIPICSI 117
285 #define SRST_GPU 120 285 #define SRST_GPU 120
286 #define SRST_HDMI 121 286 #define SRST_HDMI 121
287 #define SRST_EDP 122 287 #define SRST_EDP 122
288 #define SRST_PMU_PVTM 123 288 #define SRST_PMU_PVTM 123
289 #define SRST_CORE_PVTM 124 289 #define SRST_CORE_PVTM 124
290 #define SRST_GPU_PVTM 125 290 #define SRST_GPU_PVTM 125
291 #define SRST_GPU_SYS 126 291 #define SRST_GPU_SYS 126
292 #define SRST_GPU_MEM_NIU 127 292 #define SRST_GPU_MEM_NIU 127
293 293
294 #define SRST_MMC0 128 294 #define SRST_MMC0 128
295 #define SRST_SDIO0 129 295 #define SRST_SDIO0 129
296 #define SRST_EMMC 131 296 #define SRST_EMMC 131
297 #define SRST_USBOTG_AHB 132 297 #define SRST_USBOTG_AHB 132
298 #define SRST_USBOTG_PHY 133 298 #define SRST_USBOTG_PHY 133
299 #define SRST_USBOTG_CON 134 299 #define SRST_USBOTG_CON 134
300 #define SRST_USBHOST0_AHB 135 300 #define SRST_USBHOST0_AHB 135
301 #define SRST_USBHOST0_PHY 136 301 #define SRST_USBHOST0_PHY 136
302 #define SRST_USBHOST0_CON 137 302 #define SRST_USBHOST0_CON 137
303 #define SRST_USBOTG_UTMI 138 303 #define SRST_USBOTG_UTMI 138
304 #define SRST_USBHOST1_UTMI 139 304 #define SRST_USBHOST1_UTMI 139
305 #define SRST_USB_ADP 141 305 #define SRST_USB_ADP 141
306 306
307 #define SRST_CORESIGHT 144 307 #define SRST_CORESIGHT 144
308 #define SRST_PD_CORE_AHB_NOC 145 308 #define SRST_PD_CORE_AHB_NOC 145
309 #define SRST_PD_CORE_APB_NOC 146 309 #define SRST_PD_CORE_APB_NOC 146
310 #define SRST_GIC 148 310 #define SRST_GIC 148
311 #define SRST_LCDC_PWM0 149 311 #define SRST_LCDC_PWM0 149
312 #define SRST_RGA_H2P_BRG 153 312 #define SRST_RGA_H2P_BRG 153
313 #define SRST_VIDEO 154 313 #define SRST_VIDEO 154
314 #define SRST_GPU_CFG_NIU 157 314 #define SRST_GPU_CFG_NIU 157
315 #define SRST_TSADC 159 315 #define SRST_TSADC 159
316 316
317 #define SRST_DDRPHY0 160 317 #define SRST_DDRPHY0 160
318 #define SRST_DDRPHY0_APB 161 318 #define SRST_DDRPHY0_APB 161
319 #define SRST_DDRCTRL0 162 319 #define SRST_DDRCTRL0 162
320 #define SRST_DDRCTRL0_APB 163 320 #define SRST_DDRCTRL0_APB 163
321 #define SRST_VIDEO_NIU 165 321 #define SRST_VIDEO_NIU 165
322 #define SRST_VIDEO_NIU_AHB 167 322 #define SRST_VIDEO_NIU_AHB 167
323 #define SRST_DDRMSCH0 170 323 #define SRST_DDRMSCH0 170
324 #define SRST_PDBUS_AHB 173 324 #define SRST_PDBUS_AHB 173
325 #define SRST_CRYPTO 174 325 #define SRST_CRYPTO 174
326 326
327 #define SRST_UART0 179 327 #define SRST_UART0 179
328 #define SRST_UART1 180 328 #define SRST_UART1 180
329 #define SRST_UART2 181 329 #define SRST_UART2 181
330 #define SRST_UART3 182 330 #define SRST_UART3 182
331 #define SRST_UART4 183 331 #define SRST_UART4 183
332 #define SRST_SIMC 186 332 #define SRST_SIMC 186
333 #define SRST_TSP 188 333 #define SRST_TSP 188
334 #define SRST_TSP_CLKIN0 189 334 #define SRST_TSP_CLKIN0 189
335 335
336 #define SRST_CORE_L0 192 336 #define SRST_CORE_L0 192
337 #define SRST_CORE_L1 193 337 #define SRST_CORE_L1 193
338 #define SRST_CORE_L2 194 338 #define SRST_CORE_L2 194
339 #define SRST_CORE_L3 195 339 #define SRST_CORE_L3 195
340 #define SRST_CORE_L0_PO 195 340 #define SRST_CORE_L0_PO 195
341 #define SRST_CORE_L1_PO 197 341 #define SRST_CORE_L1_PO 197
342 #define SRST_CORE_L2_PO 198 342 #define SRST_CORE_L2_PO 198
343 #define SRST_CORE_L3_PO 199 343 #define SRST_CORE_L3_PO 199
344 #define SRST_L2_L 200 344 #define SRST_L2_L 200
345 #define SRST_ADB_L 201 345 #define SRST_ADB_L 201
346 #define SRST_PD_CORE_L_NIU 202 346 #define SRST_PD_CORE_L_NIU 202
347 #define SRST_CCI_SYS 203 347 #define SRST_CCI_SYS 203
348 #define SRST_CCI_DDR 204 348 #define SRST_CCI_DDR 204
349 #define SRST_CCI 205 349 #define SRST_CCI 205
350 #define SRST_SOCDBG_L 206 350 #define SRST_SOCDBG_L 206
351 #define SRST_CORE_L_DBG 207 351 #define SRST_CORE_L_DBG 207
352 352
353 #define SRST_CORE_B0_NC 208 353 #define SRST_CORE_B0_NC 208
354 #define SRST_CORE_B0_PO_NC 209 354 #define SRST_CORE_B0_PO_NC 209
355 #define SRST_L2_B_NC 210 355 #define SRST_L2_B_NC 210
356 #define SRST_ADB_B_NC 211 356 #define SRST_ADB_B_NC 211
357 #define SRST_PD_CORE_B_NIU_NC 212 357 #define SRST_PD_CORE_B_NIU_NC 212
358 #define SRST_PDBUS_STRSYS_NC 213 358 #define SRST_PDBUS_STRSYS_NC 213
359 #define SRST_CORE_L0_NC 214 359 #define SRST_CORE_L0_NC 214
360 #define SRST_CORE_L0_PO_NC 215 360 #define SRST_CORE_L0_PO_NC 215
361 #define SRST_L2_L_NC 216 361 #define SRST_L2_L_NC 216
362 #define SRST_ADB_L_NC 217 362 #define SRST_ADB_L_NC 217
363 #define SRST_PD_CORE_L_NIU_NC 218 363 #define SRST_PD_CORE_L_NIU_NC 218
364 #define SRST_CCI_SYS_NC 219 364 #define SRST_CCI_SYS_NC 219
365 #define SRST_CCI_DDR_NC 220 365 #define SRST_CCI_DDR_NC 220
366 #define SRST_CCI_NC 221 366 #define SRST_CCI_NC 221
367 #define SRST_TRACE_NC 222 367 #define SRST_TRACE_NC 222
368 368
369 #define SRST_TIMER00 224 369 #define SRST_TIMER00 224
370 #define SRST_TIMER01 225 370 #define SRST_TIMER01 225
371 #define SRST_TIMER02 226 371 #define SRST_TIMER02 226
372 #define SRST_TIMER03 227 372 #define SRST_TIMER03 227
373 #define SRST_TIMER04 228 373 #define SRST_TIMER04 228
374 #define SRST_TIMER05 229 374 #define SRST_TIMER05 229
375 #define SRST_TIMER10 230 375 #define SRST_TIMER10 230
376 #define SRST_TIMER11 231 376 #define SRST_TIMER11 231
377 #define SRST_TIMER12 232 377 #define SRST_TIMER12 232
378 #define SRST_TIMER13 233 378 #define SRST_TIMER13 233
379 #define SRST_TIMER14 234 379 #define SRST_TIMER14 234
380 #define SRST_TIMER15 235 380 #define SRST_TIMER15 235
381 #define SRST_TIMER0_APB 236 381 #define SRST_TIMER0_APB 236
382 #define SRST_TIMER1_APB 237 382 #define SRST_TIMER1_APB 237
383 383
384 #endif 384 #endif
385 385
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.