1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) * 1 2 /* 3 * Copyright (C) 2019 SiFive, Inc. 4 * Wesley Terpstra 5 * Paul Walmsley 6 * Zong Li 7 */ 8 9 #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_ 10 #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_ 11 12 /* Clock indexes for use by Device Tree data a 13 14 #define FU740_PRCI_CLK_COREPLL 0 15 #define FU740_PRCI_CLK_DDRPLL 1 16 #define FU740_PRCI_CLK_GEMGXLPLL 2 17 #define FU740_PRCI_CLK_DVFSCOREPLL 3 18 #define FU740_PRCI_CLK_HFPCLKPLL 4 19 #define FU740_PRCI_CLK_CLTXPLL 5 20 #define FU740_PRCI_CLK_TLCLK 6 21 #define FU740_PRCI_CLK_PCLK 7 22 #define FU740_PRCI_CLK_PCIE_AUX 8 23 24 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PR 25
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