1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 1 2 /* 3 * Copyright (C) 2021 Emil Renner Berthing <ke 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AU 7 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AU 8 9 #define JH7100_AUDCLK_ADC_MCLK 0 10 #define JH7100_AUDCLK_I2S1_MCLK 1 11 #define JH7100_AUDCLK_I2SADC_APB 2 12 #define JH7100_AUDCLK_I2SADC_BCLK 3 13 #define JH7100_AUDCLK_I2SADC_BCLK_N 4 14 #define JH7100_AUDCLK_I2SADC_LRCLK 5 15 #define JH7100_AUDCLK_PDM_APB 6 16 #define JH7100_AUDCLK_PDM_MCLK 7 17 #define JH7100_AUDCLK_I2SVAD_APB 8 18 #define JH7100_AUDCLK_SPDIF 9 19 #define JH7100_AUDCLK_SPDIF_APB 10 20 #define JH7100_AUDCLK_PWMDAC_APB 11 21 #define JH7100_AUDCLK_DAC_MCLK 12 22 #define JH7100_AUDCLK_I2SDAC_APB 13 23 #define JH7100_AUDCLK_I2SDAC_BCLK 14 24 #define JH7100_AUDCLK_I2SDAC_BCLK_N 15 25 #define JH7100_AUDCLK_I2SDAC_LRCLK 16 26 #define JH7100_AUDCLK_I2S1_APB 17 27 #define JH7100_AUDCLK_I2S1_BCLK 18 28 #define JH7100_AUDCLK_I2S1_BCLK_N 19 29 #define JH7100_AUDCLK_I2S1_LRCLK 20 30 #define JH7100_AUDCLK_I2SDAC16K_APB 21 31 #define JH7100_AUDCLK_APB0_BUS 22 32 #define JH7100_AUDCLK_DMA1P_AHB 23 33 #define JH7100_AUDCLK_USB_APB 24 34 #define JH7100_AUDCLK_USB_LPM 25 35 #define JH7100_AUDCLK_USB_STB 26 36 #define JH7100_AUDCLK_APB_EN 27 37 #define JH7100_AUDCLK_VAD_MEM 28 38 39 #define JH7100_AUDCLK_END 29 40 41 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_ 42
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