1 /* SPDX-License-Identifier: GPL-2.0 */ << 2 /* 1 /* 3 * This header provides constants clk index ST 2 * This header provides constants clk index STMicroelectronics 4 * STiH418 SoC. 3 * STiH418 SoC. 5 */ 4 */ 6 #ifndef _DT_BINDINGS_CLK_STIH418 5 #ifndef _DT_BINDINGS_CLK_STIH418 7 #define _DT_BINDINGS_CLK_STIH418 6 #define _DT_BINDINGS_CLK_STIH418 8 7 9 #include "stih410-clks.h" 8 #include "stih410-clks.h" 10 9 11 /* STiH418 introduces new clock outputs compar 10 /* STiH418 introduces new clock outputs compared to STiH410 */ 12 11 13 /* CLOCKGEN C0 */ 12 /* CLOCKGEN C0 */ 14 #define CLK_PROC_BDISP_0 14 13 #define CLK_PROC_BDISP_0 14 15 #define CLK_PROC_BDISP_1 15 14 #define CLK_PROC_BDISP_1 15 16 #define CLK_TX_ICN_1 23 15 #define CLK_TX_ICN_1 23 17 #define CLK_ETH_PHYREF 27 16 #define CLK_ETH_PHYREF 27 18 #define CLK_PP_HEVC 35 17 #define CLK_PP_HEVC 35 19 #define CLK_CLUST_HEVC 36 18 #define CLK_CLUST_HEVC 36 20 #define CLK_HWPE_HEVC 37 19 #define CLK_HWPE_HEVC 37 21 #define CLK_FC_HEVC 38 20 #define CLK_FC_HEVC 38 22 #define CLK_PROC_MIXER 39 21 #define CLK_PROC_MIXER 39 23 #define CLK_PROC_SC 40 22 #define CLK_PROC_SC 40 24 #define CLK_AVSP_HEVC 41 23 #define CLK_AVSP_HEVC 41 25 24 26 /* CLOCKGEN D2 */ 25 /* CLOCKGEN D2 */ 27 #undef CLK_PIX_PIP 26 #undef CLK_PIX_PIP 28 #undef CLK_PIX_GDP1 27 #undef CLK_PIX_GDP1 29 #undef CLK_PIX_GDP2 28 #undef CLK_PIX_GDP2 30 #undef CLK_PIX_GDP3 29 #undef CLK_PIX_GDP3 31 #undef CLK_PIX_GDP4 30 #undef CLK_PIX_GDP4 32 31 33 #define CLK_TMDS_HDMI_DIV2 5 32 #define CLK_TMDS_HDMI_DIV2 5 34 #define CLK_VP9 47 33 #define CLK_VP9 47 35 #endif 34 #endif 36 35
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