1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * stm32fx-clock.h 3 * stm32fx-clock.h 4 * 4 * 5 * Copyright (C) 2016 STMicroelectronics 5 * Copyright (C) 2016 STMicroelectronics 6 * Author: Gabriel Fernandez for STMicroelectr 6 * Author: Gabriel Fernandez for STMicroelectronics. 7 */ 7 */ 8 8 9 /* 9 /* 10 * List of clocks which are not derived from s 10 * List of clocks which are not derived from system clock (SYSCLOCK) 11 * 11 * 12 * The index of these clocks is the secondary 12 * The index of these clocks is the secondary index of DT bindings 13 * (see Documentation/devicetree/bindings/cloc 13 * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) 14 * 14 * 15 * e.g: 15 * e.g: 16 <assigned-clocks = <&rcc 1 CLK_LSE>; 16 <assigned-clocks = <&rcc 1 CLK_LSE>; 17 */ 17 */ 18 18 19 #ifndef _DT_BINDINGS_CLK_STMFX_H 19 #ifndef _DT_BINDINGS_CLK_STMFX_H 20 #define _DT_BINDINGS_CLK_STMFX_H 20 #define _DT_BINDINGS_CLK_STMFX_H 21 21 22 #define SYSTICK 0 22 #define SYSTICK 0 23 #define FCLK 1 23 #define FCLK 1 24 #define CLK_LSI 2 24 #define CLK_LSI 2 25 #define CLK_LSE 3 25 #define CLK_LSE 3 26 #define CLK_HSE_RTC 4 26 #define CLK_HSE_RTC 4 27 #define CLK_RTC 5 27 #define CLK_RTC 5 28 #define PLL_VCO_I2S 6 28 #define PLL_VCO_I2S 6 29 #define PLL_VCO_SAI 7 29 #define PLL_VCO_SAI 7 30 #define CLK_LCD 8 30 #define CLK_LCD 8 31 #define CLK_I2S 9 31 #define CLK_I2S 9 32 #define CLK_SAI1 10 32 #define CLK_SAI1 10 33 #define CLK_SAI2 11 33 #define CLK_SAI2 11 34 #define CLK_I2SQ_PDIV 12 34 #define CLK_I2SQ_PDIV 12 35 #define CLK_SAIQ_PDIV 13 35 #define CLK_SAIQ_PDIV 13 36 #define CLK_HSI 14 36 #define CLK_HSI 14 37 #define CLK_SYSCLK 15 37 #define CLK_SYSCLK 15 38 #define CLK_F469_DSI 16 38 #define CLK_F469_DSI 16 39 39 40 #define END_PRIMARY_CLK 17 40 #define END_PRIMARY_CLK 17 41 41 42 #define CLK_HDMI_CEC 16 42 #define CLK_HDMI_CEC 16 43 #define CLK_SPDIF 17 43 #define CLK_SPDIF 17 44 #define CLK_USART1 18 44 #define CLK_USART1 18 45 #define CLK_USART2 19 45 #define CLK_USART2 19 46 #define CLK_USART3 20 46 #define CLK_USART3 20 47 #define CLK_UART4 21 47 #define CLK_UART4 21 48 #define CLK_UART5 22 48 #define CLK_UART5 22 49 #define CLK_USART6 23 49 #define CLK_USART6 23 50 #define CLK_UART7 24 50 #define CLK_UART7 24 51 #define CLK_UART8 25 51 #define CLK_UART8 25 52 #define CLK_I2C1 26 52 #define CLK_I2C1 26 53 #define CLK_I2C2 27 53 #define CLK_I2C2 27 54 #define CLK_I2C3 28 54 #define CLK_I2C3 28 55 #define CLK_I2C4 29 55 #define CLK_I2C4 29 56 #define CLK_LPTIMER 30 56 #define CLK_LPTIMER 30 57 #define CLK_PLL_SRC 31 57 #define CLK_PLL_SRC 31 58 #define CLK_DFSDM1 32 58 #define CLK_DFSDM1 32 59 #define CLK_ADFSDM1 33 59 #define CLK_ADFSDM1 33 60 #define CLK_F769_DSI 34 60 #define CLK_F769_DSI 34 61 #define END_PRIMARY_CLK_F7 35 61 #define END_PRIMARY_CLK_F7 35 62 62 63 #endif 63 #endif 64 64
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