1 /* 1 2 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie. 3 * 4 * This file is dual-licensed: you can use it 5 * of the GPL or the X11 license, at your opti 6 * licensing only applies to this file, and no 7 * whole. 8 * 9 * a) This file is free software; you can red 10 * modify it under the terms of the GNU Ge 11 * published by the Free Software Foundati 12 * License, or (at your option) any later 13 * 14 * This file is distributed in the hope th 15 * but WITHOUT ANY WARRANTY; without even 16 * MERCHANTABILITY or FITNESS FOR A PARTIC 17 * GNU General Public License for more det 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of c 22 * obtaining a copy of this software and a 23 * files (the "Software"), to deal in the 24 * restriction, including without limitati 25 * copy, modify, merge, publish, distribut 26 * sell copies of the Software, and to per 27 * Software is furnished to do so, subject 28 * conditions: 29 * 30 * The above copyright notice and this per 31 * included in all copies or substantial p 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHO 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L 35 * OF MERCHANTABILITY, FITNESS FOR A PARTI 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE 38 * WHETHER IN AN ACTION OF CONTRACT, TORT 39 * FROM, OUT OF OR IN CONNECTION WITH THE 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 #ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ 44 #define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ 45 46 #define CLK_PLL_PERIPH 6 47 48 #define CLK_PLL_DE 9 49 50 #define CLK_C0CPUX 11 51 #define CLK_C1CPUX 12 52 53 #define CLK_BUS_MIPI_DSI 19 54 #define CLK_BUS_SS 20 55 #define CLK_BUS_DMA 21 56 #define CLK_BUS_MMC0 22 57 #define CLK_BUS_MMC1 23 58 #define CLK_BUS_MMC2 24 59 #define CLK_BUS_NAND 25 60 #define CLK_BUS_DRAM 26 61 #define CLK_BUS_EMAC 27 62 #define CLK_BUS_HSTIMER 28 63 #define CLK_BUS_SPI0 29 64 #define CLK_BUS_SPI1 30 65 #define CLK_BUS_OTG 31 66 #define CLK_BUS_EHCI0 32 67 #define CLK_BUS_EHCI1 33 68 #define CLK_BUS_OHCI0 34 69 70 #define CLK_BUS_VE 35 71 #define CLK_BUS_TCON0 36 72 #define CLK_BUS_TCON1 37 73 #define CLK_BUS_CSI 38 74 #define CLK_BUS_HDMI 39 75 #define CLK_BUS_DE 40 76 #define CLK_BUS_GPU 41 77 #define CLK_BUS_MSGBOX 42 78 #define CLK_BUS_SPINLOCK 43 79 80 #define CLK_BUS_SPDIF 44 81 #define CLK_BUS_PIO 45 82 #define CLK_BUS_I2S0 46 83 #define CLK_BUS_I2S1 47 84 #define CLK_BUS_I2S2 48 85 #define CLK_BUS_TDM 49 86 87 #define CLK_BUS_I2C0 50 88 #define CLK_BUS_I2C1 51 89 #define CLK_BUS_I2C2 52 90 #define CLK_BUS_UART0 53 91 #define CLK_BUS_UART1 54 92 #define CLK_BUS_UART2 55 93 #define CLK_BUS_UART3 56 94 #define CLK_BUS_UART4 57 95 96 #define CLK_NAND 59 97 #define CLK_MMC0 60 98 #define CLK_MMC0_SAMPLE 61 99 #define CLK_MMC0_OUTPUT 62 100 #define CLK_MMC1 63 101 #define CLK_MMC1_SAMPLE 64 102 #define CLK_MMC1_OUTPUT 65 103 #define CLK_MMC2 66 104 #define CLK_MMC2_SAMPLE 67 105 #define CLK_MMC2_OUTPUT 68 106 #define CLK_SS 69 107 #define CLK_SPI0 70 108 #define CLK_SPI1 71 109 #define CLK_I2S0 72 110 #define CLK_I2S1 73 111 #define CLK_I2S2 74 112 #define CLK_TDM 75 113 #define CLK_SPDIF 76 114 #define CLK_USB_PHY0 77 115 #define CLK_USB_PHY1 78 116 #define CLK_USB_HSIC 79 117 #define CLK_USB_HSIC_12M 80 118 #define CLK_USB_OHCI0 81 119 120 #define CLK_DRAM_VE 83 121 #define CLK_DRAM_CSI 84 122 123 #define CLK_TCON0 85 124 #define CLK_TCON1 86 125 #define CLK_CSI_MISC 87 126 #define CLK_MIPI_CSI 88 127 #define CLK_CSI_MCLK 89 128 #define CLK_CSI_SCLK 90 129 #define CLK_VE 91 130 #define CLK_AVS 92 131 #define CLK_HDMI 93 132 #define CLK_HDMI_SLOW 94 133 134 #define CLK_MIPI_DSI0 96 135 #define CLK_MIPI_DSI1 97 136 #define CLK_GPU_CORE 98 137 #define CLK_GPU_MEMORY 99 138 #define CLK_GPU_HYD 100 139 140 #endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ 141
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