1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (C) Sunplus Technology Co., Ltd. 3 * Copyright (C) Sunplus Technology Co., Ltd. 4 * All rights reserved. 4 * All rights reserved. 5 */ 5 */ 6 #ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 6 #ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 7 #define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 7 #define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 8 8 9 /* gates */ 9 /* gates */ 10 #define CLK_RTC 0 10 #define CLK_RTC 0 11 #define CLK_OTPRX 1 11 #define CLK_OTPRX 1 12 #define CLK_NOC 2 12 #define CLK_NOC 2 13 #define CLK_BR 3 13 #define CLK_BR 3 14 #define CLK_SPIFL 4 14 #define CLK_SPIFL 4 15 #define CLK_PERI0 5 15 #define CLK_PERI0 5 16 #define CLK_PERI1 6 16 #define CLK_PERI1 6 17 #define CLK_STC0 7 17 #define CLK_STC0 7 18 #define CLK_STC_AV0 8 18 #define CLK_STC_AV0 8 19 #define CLK_STC_AV1 9 19 #define CLK_STC_AV1 9 20 #define CLK_STC_AV2 10 20 #define CLK_STC_AV2 10 21 #define CLK_UA0 11 21 #define CLK_UA0 11 22 #define CLK_UA1 12 22 #define CLK_UA1 12 23 #define CLK_UA2 13 23 #define CLK_UA2 13 24 #define CLK_UA3 14 24 #define CLK_UA3 14 25 #define CLK_UA4 15 25 #define CLK_UA4 15 26 #define CLK_HWUA 16 26 #define CLK_HWUA 16 27 #define CLK_DDC0 17 27 #define CLK_DDC0 17 28 #define CLK_UADMA 18 28 #define CLK_UADMA 18 29 #define CLK_CBDMA0 19 29 #define CLK_CBDMA0 19 30 #define CLK_CBDMA1 20 30 #define CLK_CBDMA1 20 31 #define CLK_SPI_COMBO_0 21 31 #define CLK_SPI_COMBO_0 21 32 #define CLK_SPI_COMBO_1 22 32 #define CLK_SPI_COMBO_1 22 33 #define CLK_SPI_COMBO_2 23 33 #define CLK_SPI_COMBO_2 23 34 #define CLK_SPI_COMBO_3 24 34 #define CLK_SPI_COMBO_3 24 35 #define CLK_AUD 25 35 #define CLK_AUD 25 36 #define CLK_USBC0 26 36 #define CLK_USBC0 26 37 #define CLK_USBC1 27 37 #define CLK_USBC1 27 38 #define CLK_UPHY0 28 38 #define CLK_UPHY0 28 39 #define CLK_UPHY1 29 39 #define CLK_UPHY1 29 40 #define CLK_I2CM0 30 40 #define CLK_I2CM0 30 41 #define CLK_I2CM1 31 41 #define CLK_I2CM1 31 42 #define CLK_I2CM2 32 42 #define CLK_I2CM2 32 43 #define CLK_I2CM3 33 43 #define CLK_I2CM3 33 44 #define CLK_PMC 34 44 #define CLK_PMC 34 45 #define CLK_CARD_CTL0 35 45 #define CLK_CARD_CTL0 35 46 #define CLK_CARD_CTL1 36 46 #define CLK_CARD_CTL1 36 47 #define CLK_CARD_CTL4 37 47 #define CLK_CARD_CTL4 37 48 #define CLK_BCH 38 48 #define CLK_BCH 38 49 #define CLK_DDFCH 39 49 #define CLK_DDFCH 39 50 #define CLK_CSIIW0 40 50 #define CLK_CSIIW0 40 51 #define CLK_CSIIW1 41 51 #define CLK_CSIIW1 41 52 #define CLK_MIPICSI0 42 52 #define CLK_MIPICSI0 42 53 #define CLK_MIPICSI1 43 53 #define CLK_MIPICSI1 43 54 #define CLK_HDMI_TX 44 54 #define CLK_HDMI_TX 44 55 #define CLK_VPOST 45 55 #define CLK_VPOST 45 56 #define CLK_TGEN 46 56 #define CLK_TGEN 46 57 #define CLK_DMIX 47 57 #define CLK_DMIX 47 58 #define CLK_TCON 48 58 #define CLK_TCON 48 59 #define CLK_GPIO 49 59 #define CLK_GPIO 49 60 #define CLK_MAILBOX 50 60 #define CLK_MAILBOX 50 61 #define CLK_SPIND 51 61 #define CLK_SPIND 51 62 #define CLK_I2C2CBUS 52 62 #define CLK_I2C2CBUS 52 63 #define CLK_SEC 53 63 #define CLK_SEC 53 64 #define CLK_DVE 54 64 #define CLK_DVE 54 65 #define CLK_GPOST0 55 65 #define CLK_GPOST0 55 66 #define CLK_OSD0 56 66 #define CLK_OSD0 56 67 #define CLK_DISP_PWM 57 67 #define CLK_DISP_PWM 57 68 #define CLK_UADBG 58 68 #define CLK_UADBG 58 69 #define CLK_FIO_CTL 59 69 #define CLK_FIO_CTL 59 70 #define CLK_FPGA 60 70 #define CLK_FPGA 60 71 #define CLK_L2SW 61 71 #define CLK_L2SW 61 72 #define CLK_ICM 62 72 #define CLK_ICM 62 73 #define CLK_AXI_GLOBAL 63 73 #define CLK_AXI_GLOBAL 63 74 74 75 /* plls */ 75 /* plls */ 76 #define PLL_A 64 76 #define PLL_A 64 77 #define PLL_E 65 77 #define PLL_E 65 78 #define PLL_E_2P5 66 78 #define PLL_E_2P5 66 79 #define PLL_E_25 67 79 #define PLL_E_25 67 80 #define PLL_E_112P5 68 80 #define PLL_E_112P5 68 81 #define PLL_F 69 81 #define PLL_F 69 82 #define PLL_TV 70 82 #define PLL_TV 70 83 #define PLL_TV_A 71 83 #define PLL_TV_A 71 84 #define PLL_SYS 72 84 #define PLL_SYS 72 85 85 86 #define CLK_MAX 73 86 #define CLK_MAX 73 87 87 88 #endif 88 #endif 89 89
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