1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* Copyright (c) 2018, NVIDIA CORPORATION. All 3 4 #ifndef __ABI_MACH_T194_CLOCK_H 5 #define __ABI_MACH_T194_CLOCK_H 6 7 #define TEGRA194_CLK_ACTMON 8 #define TEGRA194_CLK_ADSP 9 #define TEGRA194_CLK_ADSPNEON 10 #define TEGRA194_CLK_AHUB 11 #define TEGRA194_CLK_APB2APE 12 #define TEGRA194_CLK_APE 13 #define TEGRA194_CLK_AUD_MCLK 14 #define TEGRA194_CLK_AXI_CBB 15 #define TEGRA194_CLK_CAN1 16 #define TEGRA194_CLK_CAN1_HOST 17 #define TEGRA194_CLK_CAN2 18 #define TEGRA194_CLK_CAN2_HOST 19 #define TEGRA194_CLK_CEC 20 #define TEGRA194_CLK_CLK_M 21 #define TEGRA194_CLK_DMIC1 22 #define TEGRA194_CLK_DMIC2 23 #define TEGRA194_CLK_DMIC3 24 #define TEGRA194_CLK_DMIC4 25 #define TEGRA194_CLK_DPAUX 26 #define TEGRA194_CLK_DPAUX1 27 #define TEGRA194_CLK_ACLK 28 #define TEGRA194_CLK_MSS_ENCRYPT 29 #define TEGRA194_CLK_EQOS_RX_INPUT 30 #define TEGRA194_CLK_IQC2 31 #define TEGRA194_CLK_AON_APB 32 #define TEGRA194_CLK_AON_NIC 33 #define TEGRA194_CLK_AON_CPU_NIC 34 #define TEGRA194_CLK_PLLA1 35 #define TEGRA194_CLK_DSPK1 36 #define TEGRA194_CLK_DSPK2 37 #define TEGRA194_CLK_EMC 38 #define TEGRA194_CLK_EQOS_AXI 39 #define TEGRA194_CLK_EQOS_PTP_REF 40 #define TEGRA194_CLK_EQOS_RX 41 #define TEGRA194_CLK_EQOS_TX 42 #define TEGRA194_CLK_EXTPERIPH1 43 #define TEGRA194_CLK_EXTPERIPH2 44 #define TEGRA194_CLK_EXTPERIPH3 45 #define TEGRA194_CLK_EXTPERIPH4 46 #define TEGRA194_CLK_FUSE 47 #define TEGRA194_CLK_GPCCLK 48 #define TEGRA194_CLK_GPU_PWR 49 #define TEGRA194_CLK_HDA 50 #define TEGRA194_CLK_HDA2CODEC_2X 51 #define TEGRA194_CLK_HDA2HDMICODEC 52 #define TEGRA194_CLK_HOST1X 53 #define TEGRA194_CLK_HSIC_TRK 54 #define TEGRA194_CLK_I2C1 55 #define TEGRA194_CLK_I2C2 56 #define TEGRA194_CLK_I2C3 57 #define TEGRA194_CLK_I2C4 58 #define TEGRA194_CLK_I2C6 59 #define TEGRA194_CLK_I2C7 60 #define TEGRA194_CLK_I2C8 61 #define TEGRA194_CLK_I2C9 62 #define TEGRA194_CLK_I2S1 63 #define TEGRA194_CLK_I2S1_SYNC_INPUT 64 #define TEGRA194_CLK_I2S2 65 #define TEGRA194_CLK_I2S2_SYNC_INPUT 66 #define TEGRA194_CLK_I2S3 67 #define TEGRA194_CLK_I2S3_SYNC_INPUT 68 #define TEGRA194_CLK_I2S4 69 #define TEGRA194_CLK_I2S4_SYNC_INPUT 70 #define TEGRA194_CLK_I2S5 71 #define TEGRA194_CLK_I2S5_SYNC_INPUT 72 #define TEGRA194_CLK_I2S6 73 #define TEGRA194_CLK_I2S6_SYNC_INPUT 74 #define TEGRA194_CLK_IQC1 75 #define TEGRA194_CLK_ISP 76 #define TEGRA194_CLK_KFUSE 77 #define TEGRA194_CLK_MAUD 78 #define TEGRA194_CLK_MIPI_CAL 79 #define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 80 #define TEGRA194_CLK_MPHY_L0_RX_ANA 81 #define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 82 #define TEGRA194_CLK_MPHY_L0_RX_SYMB 83 #define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 84 #define TEGRA194_CLK_MPHY_L0_TX_SYMB 85 #define TEGRA194_CLK_MPHY_L1_RX_ANA 86 #define TEGRA194_CLK_MPHY_TX_1MHZ_REF 87 #define TEGRA194_CLK_NVCSI 88 #define TEGRA194_CLK_NVCSILP 89 #define TEGRA194_CLK_NVDEC 90 #define TEGRA194_CLK_NVDISPLAYHUB 91 #define TEGRA194_CLK_NVDISPLAY_DISP 92 #define TEGRA194_CLK_NVDISPLAY_P0 93 #define TEGRA194_CLK_NVDISPLAY_P1 94 #define TEGRA194_CLK_NVDISPLAY_P2 95 #define TEGRA194_CLK_NVENC 96 #define TEGRA194_CLK_NVJPG 97 #define TEGRA194_CLK_OSC 98 #define TEGRA194_CLK_AON_TOUCH 99 #define TEGRA194_CLK_PLLA 100 #define TEGRA194_CLK_PLLAON 101 #define TEGRA194_CLK_PLLD 102 #define TEGRA194_CLK_PLLD2 103 #define TEGRA194_CLK_PLLD3 104 #define TEGRA194_CLK_PLLDP 105 #define TEGRA194_CLK_PLLD4 106 #define TEGRA194_CLK_PLLE 107 #define TEGRA194_CLK_PLLP 108 #define TEGRA194_CLK_PLLP_OUT0 109 #define TEGRA194_CLK_UTMIPLL 110 #define TEGRA194_CLK_PLLA_OUT0 111 #define TEGRA194_CLK_PWM1 112 #define TEGRA194_CLK_PWM2 113 #define TEGRA194_CLK_PWM3 114 #define TEGRA194_CLK_PWM4 115 #define TEGRA194_CLK_PWM5 116 #define TEGRA194_CLK_PWM6 117 #define TEGRA194_CLK_PWM7 118 #define TEGRA194_CLK_PWM8 119 #define TEGRA194_CLK_RCE_CPU_NIC 120 #define TEGRA194_CLK_RCE_NIC 121 #define TEGRA194_CLK_SATA 122 #define TEGRA194_CLK_SATA_OOB 123 #define TEGRA194_CLK_AON_I2C_SLOW 124 #define TEGRA194_CLK_SCE_CPU_NIC 125 #define TEGRA194_CLK_SCE_NIC 126 #define TEGRA194_CLK_SDMMC1 127 #define TEGRA194_CLK_UPHY_PLL3 128 #define TEGRA194_CLK_SDMMC3 129 #define TEGRA194_CLK_SDMMC4 130 #define TEGRA194_CLK_SE 131 #define TEGRA194_CLK_SOR0_OUT 132 #define TEGRA194_CLK_SOR0_REF 133 #define TEGRA194_CLK_SOR0_PAD_CLKOUT 134 #define TEGRA194_CLK_SOR1_OUT 135 #define TEGRA194_CLK_SOR1_REF 136 #define TEGRA194_CLK_SOR1_PAD_CLKOUT 137 #define TEGRA194_CLK_SOR_SAFE 138 #define TEGRA194_CLK_IQC1_IN 139 #define TEGRA194_CLK_IQC2_IN 140 #define TEGRA194_CLK_DMIC5 141 #define TEGRA194_CLK_SPI1 142 #define TEGRA194_CLK_SPI2 143 #define TEGRA194_CLK_SPI3 144 #define TEGRA194_CLK_I2C_SLOW 145 #define TEGRA194_CLK_SYNC_DMIC1 146 #define TEGRA194_CLK_SYNC_DMIC2 147 #define TEGRA194_CLK_SYNC_DMIC3 148 #define TEGRA194_CLK_SYNC_DMIC4 149 #define TEGRA194_CLK_SYNC_DSPK1 150 #define TEGRA194_CLK_SYNC_DSPK2 151 #define TEGRA194_CLK_SYNC_I2S1 152 #define TEGRA194_CLK_SYNC_I2S2 153 #define TEGRA194_CLK_SYNC_I2S3 154 #define TEGRA194_CLK_SYNC_I2S4 155 #define TEGRA194_CLK_SYNC_I2S5 156 #define TEGRA194_CLK_SYNC_I2S6 157 #define TEGRA194_CLK_MPHY_FORCE_LS_MODE 158 #define TEGRA194_CLK_TACH 159 #define TEGRA194_CLK_TSEC 160 #define TEGRA194_CLK_TSECB 161 #define TEGRA194_CLK_UARTA 162 #define TEGRA194_CLK_UARTB 163 #define TEGRA194_CLK_UARTC 164 #define TEGRA194_CLK_UARTD 165 #define TEGRA194_CLK_UARTE 166 #define TEGRA194_CLK_UARTF 167 #define TEGRA194_CLK_UARTG 168 #define TEGRA194_CLK_UART_FST_MIPI_CAL 169 #define TEGRA194_CLK_UFSDEV_REF 170 #define TEGRA194_CLK_UFSHC 171 #define TEGRA194_CLK_USB2_TRK 172 #define TEGRA194_CLK_VI 173 #define TEGRA194_CLK_VIC 174 #define TEGRA194_CLK_PVA0_AXI 175 #define TEGRA194_CLK_PVA0_VPS0 176 #define TEGRA194_CLK_PVA0_VPS1 177 #define TEGRA194_CLK_PVA1_AXI 178 #define TEGRA194_CLK_PVA1_VPS0 179 #define TEGRA194_CLK_PVA1_VPS1 180 #define TEGRA194_CLK_DLA0_FALCON 181 #define TEGRA194_CLK_DLA0_CORE 182 #define TEGRA194_CLK_DLA1_FALCON 183 #define TEGRA194_CLK_DLA1_CORE 184 #define TEGRA194_CLK_SOR2_OUT 185 #define TEGRA194_CLK_SOR2_REF 186 #define TEGRA194_CLK_SOR2_PAD_CLKOUT 187 #define TEGRA194_CLK_SOR3_OUT 188 #define TEGRA194_CLK_SOR3_REF 189 #define TEGRA194_CLK_SOR3_PAD_CLKOUT 190 #define TEGRA194_CLK_NVDISPLAY_P3 191 #define TEGRA194_CLK_DPAUX2 192 #define TEGRA194_CLK_DPAUX3 193 #define TEGRA194_CLK_NVDEC1 194 #define TEGRA194_CLK_NVENC1 195 #define TEGRA194_CLK_SE_FREE 196 #define TEGRA194_CLK_UARTH 197 #define TEGRA194_CLK_FUSE_SERIAL 198 #define TEGRA194_CLK_QSPI0 199 #define TEGRA194_CLK_QSPI1 200 #define TEGRA194_CLK_QSPI0_PM 201 #define TEGRA194_CLK_QSPI1_PM 202 #define TEGRA194_CLK_VI_CONST 203 #define TEGRA194_CLK_NAFLL_BPMP 204 #define TEGRA194_CLK_NAFLL_SCE 205 #define TEGRA194_CLK_NAFLL_NVDEC 206 #define TEGRA194_CLK_NAFLL_NVJPG 207 #define TEGRA194_CLK_NAFLL_TSEC 208 #define TEGRA194_CLK_NAFLL_TSECB 209 #define TEGRA194_CLK_NAFLL_VI 210 #define TEGRA194_CLK_NAFLL_SE 211 #define TEGRA194_CLK_NAFLL_NVENC 212 #define TEGRA194_CLK_NAFLL_ISP 213 #define TEGRA194_CLK_NAFLL_VIC 214 #define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 215 #define TEGRA194_CLK_NAFLL_AXICBB 216 #define TEGRA194_CLK_NAFLL_DLA 217 #define TEGRA194_CLK_NAFLL_PVA_CORE 218 #define TEGRA194_CLK_NAFLL_PVA_VPS 219 #define TEGRA194_CLK_NAFLL_CVNAS 220 #define TEGRA194_CLK_NAFLL_RCE 221 #define TEGRA194_CLK_NAFLL_NVENC1 222 #define TEGRA194_CLK_NAFLL_DLA_FALCON 223 #define TEGRA194_CLK_NAFLL_NVDEC1 224 #define TEGRA194_CLK_NAFLL_GPU 225 #define TEGRA194_CLK_SDMMC_LEGACY_TM 226 #define TEGRA194_CLK_PEX0_CORE_0 227 #define TEGRA194_CLK_PEX0_CORE_1 228 #define TEGRA194_CLK_PEX0_CORE_2 229 #define TEGRA194_CLK_PEX0_CORE_3 230 #define TEGRA194_CLK_PEX0_CORE_4 231 #define TEGRA194_CLK_PEX1_CORE_5 232 #define TEGRA194_CLK_PEX_REF1 233 #define TEGRA194_CLK_PEX_REF2 234 #define TEGRA194_CLK_CSI_A 235 #define TEGRA194_CLK_CSI_B 236 #define TEGRA194_CLK_CSI_C 237 #define TEGRA194_CLK_CSI_D 238 #define TEGRA194_CLK_CSI_E 239 #define TEGRA194_CLK_CSI_F 240 #define TEGRA194_CLK_CSI_G 241 #define TEGRA194_CLK_CSI_H 242 #define TEGRA194_CLK_PLLC4 243 #define TEGRA194_CLK_PLLC4_OUT 244 #define TEGRA194_CLK_PLLC4_OUT1 245 #define TEGRA194_CLK_PLLC4_OUT2 246 #define TEGRA194_CLK_PLLC4_MUXED 247 #define TEGRA194_CLK_PLLC4_VCO_DIV2 248 #define TEGRA194_CLK_CSI_A_PAD 249 #define TEGRA194_CLK_CSI_B_PAD 250 #define TEGRA194_CLK_CSI_C_PAD 251 #define TEGRA194_CLK_CSI_D_PAD 252 #define TEGRA194_CLK_CSI_E_PAD 253 #define TEGRA194_CLK_CSI_F_PAD 254 #define TEGRA194_CLK_CSI_G_PAD 255 #define TEGRA194_CLK_CSI_H_PAD 256 #define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 257 #define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 258 #define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 259 #define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 260 #define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 261 #define TEGRA194_CLK_XUSB_CORE_DEV 262 #define TEGRA194_CLK_XUSB_CORE_MUX 263 #define TEGRA194_CLK_XUSB_CORE_HOST 264 #define TEGRA194_CLK_XUSB_CORE_SS 265 #define TEGRA194_CLK_XUSB_FALCON 266 #define TEGRA194_CLK_XUSB_FALCON_HOST 267 #define TEGRA194_CLK_XUSB_FALCON_SS 268 #define TEGRA194_CLK_XUSB_FS 269 #define TEGRA194_CLK_XUSB_FS_HOST 270 #define TEGRA194_CLK_XUSB_FS_DEV 271 #define TEGRA194_CLK_XUSB_SS 272 #define TEGRA194_CLK_XUSB_SS_DEV 273 #define TEGRA194_CLK_XUSB_SS_SUPERSPEED 274 #define TEGRA194_CLK_PLLDISPHUB 275 #define TEGRA194_CLK_PLLDISPHUB_DIV 276 #define TEGRA194_CLK_NAFLL_CLUSTER0 277 #define TEGRA194_CLK_NAFLL_CLUSTER1 278 #define TEGRA194_CLK_NAFLL_CLUSTER2 279 #define TEGRA194_CLK_NAFLL_CLUSTER3 280 #define TEGRA194_CLK_CAN1_CORE 281 #define TEGRA194_CLK_CAN2_CORE 282 #define TEGRA194_CLK_PLLA1_OUT1 283 #define TEGRA194_CLK_PLLREFE_VCOOUT 284 #define TEGRA194_CLK_CLK_32K 285 #define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 286 #define TEGRA194_CLK_UTMIPLL_CLKOUT48 287 #define TEGRA194_CLK_UTMIPLL_CLKOUT480 288 #define TEGRA194_CLK_CVNAS 289 #define TEGRA194_CLK_PLLNVCSI 290 #define TEGRA194_CLK_PVA0_CPU_AXI 291 #define TEGRA194_CLK_PVA1_CPU_AXI 292 #define TEGRA194_CLK_PVA0_VPS 293 #define TEGRA194_CLK_PVA1_VPS 294 #define TEGRA194_CLK_DLA0_FALCON_MUX 295 #define TEGRA194_CLK_DLA1_FALCON_MUX 296 #define TEGRA194_CLK_DLA0_CORE_MUX 297 #define TEGRA194_CLK_DLA1_CORE_MUX 298 #define TEGRA194_CLK_UTMIPLL_HPS 299 #define TEGRA194_CLK_I2C5 300 #define TEGRA194_CLK_I2C10 301 #define TEGRA194_CLK_BPMP_CPU_NIC 302 #define TEGRA194_CLK_BPMP_APB 303 #define TEGRA194_CLK_TSC 304 #define TEGRA194_CLK_EMCSA 305 #define TEGRA194_CLK_EMCSB 306 #define TEGRA194_CLK_EMCSC 307 #define TEGRA194_CLK_EMCSD 308 #define TEGRA194_CLK_PLLC 309 #define TEGRA194_CLK_PLLC2 310 #define TEGRA194_CLK_PLLC3 311 #define TEGRA194_CLK_TSC_REF 312 #define TEGRA194_CLK_FUSE_BURN 313 #define TEGRA194_CLK_PEX0_CORE_0M 314 #define TEGRA194_CLK_PEX0_CORE_1M 315 #define TEGRA194_CLK_PEX0_CORE_2M 316 #define TEGRA194_CLK_PEX0_CORE_3M 317 #define TEGRA194_CLK_PEX0_CORE_4M 318 #define TEGRA194_CLK_PEX1_CORE_5M 319 #define TEGRA194_CLK_PLLE_HPS 320 321 #endif 322
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