1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Houlong Wei <houlong.wei@mediatek.c 5 * 6 */ 7 8 #ifndef _DT_BINDINGS_GCE_MT8173_H 9 #define _DT_BINDINGS_GCE_MT8173_H 10 11 /* GCE HW thread priority */ 12 #define CMDQ_THR_PRIO_LOWEST 0 13 #define CMDQ_THR_PRIO_HIGHEST 1 14 15 /* GCE SUBSYS */ 16 #define SUBSYS_1400XXXX 1 17 #define SUBSYS_1401XXXX 2 18 #define SUBSYS_1402XXXX 3 19 20 /* GCE HW EVENT */ 21 #define CMDQ_EVENT_DISP_OVL0_SOF 22 #define CMDQ_EVENT_DISP_OVL1_SOF 23 #define CMDQ_EVENT_DISP_RDMA0_SOF 24 #define CMDQ_EVENT_DISP_RDMA1_SOF 25 #define CMDQ_EVENT_DISP_RDMA2_SOF 26 #define CMDQ_EVENT_DISP_WDMA0_SOF 27 #define CMDQ_EVENT_DISP_WDMA1_SOF 28 #define CMDQ_EVENT_DISP_OVL0_EOF 29 #define CMDQ_EVENT_DISP_OVL1_EOF 30 #define CMDQ_EVENT_DISP_RDMA0_EOF 31 #define CMDQ_EVENT_DISP_RDMA1_EOF 32 #define CMDQ_EVENT_DISP_RDMA2_EOF 33 #define CMDQ_EVENT_DISP_WDMA0_EOF 34 #define CMDQ_EVENT_DISP_WDMA1_EOF 35 #define CMDQ_EVENT_MUTEX0_STREAM_EOF 36 #define CMDQ_EVENT_MUTEX1_STREAM_EOF 37 #define CMDQ_EVENT_MUTEX2_STREAM_EOF 38 #define CMDQ_EVENT_MUTEX3_STREAM_EOF 39 #define CMDQ_EVENT_MUTEX4_STREAM_EOF 40 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 41 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 42 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 43 44 #endif 45
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