1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Bibby Hsieh <bibby.hsieh@mediatek.c 5 * 6 */ 7 8 #ifndef _DT_BINDINGS_GCE_MT8183_H 9 #define _DT_BINDINGS_GCE_MT8183_H 10 11 #define CMDQ_NO_TIMEOUT 0xffffffff 12 13 /* GCE HW thread priority */ 14 #define CMDQ_THR_PRIO_LOWEST 0 15 #define CMDQ_THR_PRIO_HIGHEST 1 16 17 /* GCE SUBSYS */ 18 #define SUBSYS_1300XXXX 0 19 #define SUBSYS_1400XXXX 1 20 #define SUBSYS_1401XXXX 2 21 #define SUBSYS_1402XXXX 3 22 #define SUBSYS_1502XXXX 4 23 #define SUBSYS_1880XXXX 5 24 #define SUBSYS_1881XXXX 6 25 #define SUBSYS_1882XXXX 7 26 #define SUBSYS_1883XXXX 8 27 #define SUBSYS_1884XXXX 9 28 #define SUBSYS_1000XXXX 10 29 #define SUBSYS_1001XXXX 11 30 #define SUBSYS_1002XXXX 12 31 #define SUBSYS_1003XXXX 13 32 #define SUBSYS_1004XXXX 14 33 #define SUBSYS_1005XXXX 15 34 #define SUBSYS_1020XXXX 16 35 #define SUBSYS_1028XXXX 17 36 #define SUBSYS_1700XXXX 18 37 #define SUBSYS_1701XXXX 19 38 #define SUBSYS_1702XXXX 20 39 #define SUBSYS_1703XXXX 21 40 #define SUBSYS_1800XXXX 22 41 #define SUBSYS_1801XXXX 23 42 #define SUBSYS_1802XXXX 24 43 #define SUBSYS_1804XXXX 25 44 #define SUBSYS_1805XXXX 26 45 #define SUBSYS_1808XXXX 27 46 #define SUBSYS_180aXXXX 28 47 #define SUBSYS_180bXXXX 29 48 49 #define CMDQ_EVENT_DISP_RDMA0_SOF 50 #define CMDQ_EVENT_DISP_RDMA1_SOF 51 #define CMDQ_EVENT_MDP_RDMA0_SOF 52 #define CMDQ_EVENT_MDP_RSZ0_SOF 53 #define CMDQ_EVENT_MDP_RSZ1_SOF 54 #define CMDQ_EVENT_MDP_TDSHP_SOF 55 #define CMDQ_EVENT_MDP_WROT0_SOF 56 #define CMDQ_EVENT_MDP_WDMA0_SOF 57 #define CMDQ_EVENT_DISP_OVL0_SOF 58 #define CMDQ_EVENT_DISP_OVL0_2L_SOF 59 #define CMDQ_EVENT_DISP_OVL1_2L_SOF 60 #define CMDQ_EVENT_DISP_WDMA0_SOF 61 #define CMDQ_EVENT_DISP_COLOR0_SOF 62 #define CMDQ_EVENT_DISP_CCORR0_SOF 63 #define CMDQ_EVENT_DISP_AAL0_SOF 64 #define CMDQ_EVENT_DISP_GAMMA0_SOF 65 #define CMDQ_EVENT_DISP_DITHER0_SOF 66 #define CMDQ_EVENT_DISP_PWM0_SOF 67 #define CMDQ_EVENT_DISP_DSI0_SOF 68 #define CMDQ_EVENT_DISP_DPI0_SOF 69 #define CMDQ_EVENT_DISP_RSZ_SOF 70 #define CMDQ_EVENT_MDP_AAL_SOF 71 #define CMDQ_EVENT_MDP_CCORR_SOF 72 #define CMDQ_EVENT_DISP_DBI_SOF 73 #define CMDQ_EVENT_DISP_RDMA0_EOF 74 #define CMDQ_EVENT_DISP_RDMA1_EOF 75 #define CMDQ_EVENT_MDP_RDMA0_EOF 76 #define CMDQ_EVENT_MDP_RSZ0_EOF 77 #define CMDQ_EVENT_MDP_RSZ1_EOF 78 #define CMDQ_EVENT_MDP_TDSHP_EOF 79 #define CMDQ_EVENT_MDP_WROT0_EOF 80 #define CMDQ_EVENT_MDP_WDMA0_EOF 81 #define CMDQ_EVENT_DISP_OVL0_EOF 82 #define CMDQ_EVENT_DISP_OVL0_2L_EOF 83 #define CMDQ_EVENT_DISP_OVL1_2L_EOF 84 #define CMDQ_EVENT_DISP_WDMA0_EOF 85 #define CMDQ_EVENT_DISP_COLOR0_EOF 86 #define CMDQ_EVENT_DISP_CCORR0_EOF 87 #define CMDQ_EVENT_DISP_AAL0_EOF 88 #define CMDQ_EVENT_DISP_GAMMA0_EOF 89 #define CMDQ_EVENT_DISP_DITHER0_EOF 90 #define CMDQ_EVENT_DSI0_EOF 91 #define CMDQ_EVENT_DPI0_EOF 92 #define CMDQ_EVENT_DISP_RSZ_EOF 93 #define CMDQ_EVENT_MDP_AAL_EOF 94 #define CMDQ_EVENT_MDP_CCORR_EOF 95 #define CMDQ_EVENT_DBI_EOF 96 #define CMDQ_EVENT_MUTEX_STREAM_DONE0 97 #define CMDQ_EVENT_MUTEX_STREAM_DONE1 98 #define CMDQ_EVENT_MUTEX_STREAM_DONE2 99 #define CMDQ_EVENT_MUTEX_STREAM_DONE3 100 #define CMDQ_EVENT_MUTEX_STREAM_DONE4 101 #define CMDQ_EVENT_MUTEX_STREAM_DONE5 102 #define CMDQ_EVENT_MUTEX_STREAM_DONE6 103 #define CMDQ_EVENT_MUTEX_STREAM_DONE7 104 #define CMDQ_EVENT_MUTEX_STREAM_DONE8 105 #define CMDQ_EVENT_MUTEX_STREAM_DONE9 106 #define CMDQ_EVENT_MUTEX_STREAM_DONE10 107 #define CMDQ_EVENT_MUTEX_STREAM_DONE11 108 #define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVE 109 #define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVE 110 #define CMDQ_EVENT_DSI0_TE_EVENT 111 #define CMDQ_EVENT_DSI0_IRQ_EVENT 112 #define CMDQ_EVENT_DSI0_DONE_EVENT 113 #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 114 #define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 115 #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 116 #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 117 #define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PU 118 #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE 119 #define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE 120 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 121 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 122 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 123 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 124 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 125 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 126 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 127 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 128 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 129 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 130 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 131 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 132 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 133 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 134 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 135 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 136 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 137 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 138 #define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 139 #define CMDQ_EVENT_AMD_FRAME_DONE 140 #define CMDQ_EVENT_DVE_DONE 141 #define CMDQ_EVENT_WMFE_DONE 142 #define CMDQ_EVENT_RSC_DONE 143 #define CMDQ_EVENT_MFB_DONE 144 #define CMDQ_EVENT_WPE_A_DONE 145 #define CMDQ_EVENT_SPE_B_DONE 146 #define CMDQ_EVENT_OCC_DONE 147 #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 148 #define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 149 #define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 150 #define CMDQ_EVENT_VENC_CMDQ_MB_DONE 151 #define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 152 #define CMDQ_EVENT_ISP_FRAME_DONE_A 153 #define CMDQ_EVENT_ISP_FRAME_DONE_B 154 #define CMDQ_EVENT_CAMSV0_PASS1_DONE 155 #define CMDQ_EVENT_CAMSV1_PASS1_DONE 156 #define CMDQ_EVENT_CAMSV2_PASS1_DONE 157 #define CMDQ_EVENT_TSF_DONE 158 #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 159 #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 160 #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 161 #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 162 #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 163 #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 164 #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 165 #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 166 #define CMDQ_EVENT_IPU_CORE0_DONE0 167 #define CMDQ_EVENT_IPU_CORE0_DONE1 168 #define CMDQ_EVENT_IPU_CORE0_DONE2 169 #define CMDQ_EVENT_IPU_CORE0_DONE3 170 #define CMDQ_EVENT_IPU_CORE1_DONE0 171 #define CMDQ_EVENT_IPU_CORE1_DONE1 172 #define CMDQ_EVENT_IPU_CORE1_DONE2 173 #define CMDQ_EVENT_IPU_CORE1_DONE3 174 175 #endif 176
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