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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/gce/mt8192-gce.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /include/dt-bindings/gce/mt8192-gce.h (Version linux-6.12-rc7) and /include/dt-bindings/gce/mt8192-gce.h (Version linux-4.15.18)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 
  2 /*                                                
  3  * Copyright (c) 2020 MediaTek Inc.               
  4  * Author: Yongqiang Niu <yongqiang.niu@mediat    
  5  */                                               
  6                                                   
  7 #ifndef _DT_BINDINGS_GCE_MT8192_H                 
  8 #define _DT_BINDINGS_GCE_MT8192_H                 
  9                                                   
 10 /* assign timeout 0 also means default */         
 11 #define CMDQ_NO_TIMEOUT         0xffffffff        
 12 #define CMDQ_TIMEOUT_DEFAULT    1000              
 13                                                   
 14 /* GCE thread priority */                         
 15 #define CMDQ_THR_PRIO_LOWEST    0                 
 16 #define CMDQ_THR_PRIO_1         1                 
 17 #define CMDQ_THR_PRIO_2         2                 
 18 #define CMDQ_THR_PRIO_3         3                 
 19 #define CMDQ_THR_PRIO_4         4                 
 20 #define CMDQ_THR_PRIO_5         5                 
 21 #define CMDQ_THR_PRIO_6         6                 
 22 #define CMDQ_THR_PRIO_HIGHEST   7                 
 23                                                   
 24 /* CPR count in 32bit register */                 
 25 #define GCE_CPR_COUNT           1312              
 26                                                   
 27 /* GCE subsys table */                            
 28 #define SUBSYS_1300XXXX         0                 
 29 #define SUBSYS_1400XXXX         1                 
 30 #define SUBSYS_1401XXXX         2                 
 31 #define SUBSYS_1402XXXX         3                 
 32 #define SUBSYS_1502XXXX         4                 
 33 #define SUBSYS_1880XXXX         5                 
 34 #define SUBSYS_1881XXXX         6                 
 35 #define SUBSYS_1882XXXX         7                 
 36 #define SUBSYS_1883XXXX         8                 
 37 #define SUBSYS_1884XXXX         9                 
 38 #define SUBSYS_1000XXXX         10                
 39 #define SUBSYS_1001XXXX         11                
 40 #define SUBSYS_1002XXXX         12                
 41 #define SUBSYS_1003XXXX         13                
 42 #define SUBSYS_1004XXXX         14                
 43 #define SUBSYS_1005XXXX         15                
 44 #define SUBSYS_1020XXXX         16                
 45 #define SUBSYS_1028XXXX         17                
 46 #define SUBSYS_1700XXXX         18                
 47 #define SUBSYS_1701XXXX         19                
 48 #define SUBSYS_1702XXXX         20                
 49 #define SUBSYS_1703XXXX         21                
 50 #define SUBSYS_1800XXXX         22                
 51 #define SUBSYS_1801XXXX         23                
 52 #define SUBSYS_1802XXXX         24                
 53 #define SUBSYS_1804XXXX         25                
 54 #define SUBSYS_1805XXXX         26                
 55 #define SUBSYS_1808XXXX         27                
 56 #define SUBSYS_180aXXXX         28                
 57 #define SUBSYS_180bXXXX         29                
 58                                                   
 59 #define CMDQ_EVENT_VDEC_LAT_SOF_0                 
 60 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0          
 61 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1          
 62 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2          
 63 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3          
 64 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4          
 65 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5          
 66 #define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6          
 67 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0           
 68 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1           
 69 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2           
 70 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3           
 71 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_4           
 72 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_5           
 73 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_6           
 74 #define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7           
 75                                                   
 76 #define CMDQ_EVENT_ISP_FRAME_DONE_A               
 77 #define CMDQ_EVENT_ISP_FRAME_DONE_B               
 78 #define CMDQ_EVENT_ISP_FRAME_DONE_C               
 79 #define CMDQ_EVENT_CAMSV0_PASS1_DONE              
 80 #define CMDQ_EVENT_CAMSV02_PASS1_DONE             
 81 #define CMDQ_EVENT_CAMSV1_PASS1_DONE              
 82 #define CMDQ_EVENT_CAMSV2_PASS1_DONE              
 83 #define CMDQ_EVENT_CAMSV3_PASS1_DONE              
 84 #define CMDQ_EVENT_MRAW_0_PASS1_DONE              
 85 #define CMDQ_EVENT_MRAW_1_PASS1_DONE              
 86 #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL          
 87 #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL          
 88 #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL          
 89 #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL          
 90 #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL          
 91 #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL          
 92 #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL          
 93 #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL          
 94 #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL          
 95 #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL          
 96 #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL         
 97 #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL         
 98 #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL         
 99 #define CMDQ_EVENT_TG_OVRUN_A_INT                 
100 #define CMDQ_EVENT_DMA_R1_ERROR_A_INT             
101 #define CMDQ_EVENT_TG_OVRUN_B_INT                 
102 #define CMDQ_EVENT_DMA_R1_ERROR_B_INT             
103 #define CMDQ_EVENT_TG_OVRUN_C_INT                 
104 #define CMDQ_EVENT_DMA_R1_ERROR_C_INT             
105 #define CMDQ_EVENT_TG_OVRUN_M0_INT                
106 #define CMDQ_EVENT_DMA_R1_ERROR_M0_INT            
107 #define CMDQ_EVENT_TG_GRABERR_M0_INT              
108 #define CMDQ_EVENT_TG_GRABERR_M1_INT              
109 #define CMDQ_EVENT_TG_GRABERR_A_INT               
110 #define CMDQ_EVENT_CQ_VR_SNAP_A_INT               
111 #define CMDQ_EVENT_TG_GRABERR_B_INT               
112 #define CMDQ_EVENT_CQ_VR_SNAP_B_INT               
113 #define CMDQ_EVENT_TG_GRABERR_C_INT               
114 #define CMDQ_EVENT_CQ_VR_SNAP_C_INT               
115                                                   
116 #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE           
117 #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE           
118 #define CMDQ_EVENT_JPGENC_CMDQ_DONE               
119 #define CMDQ_EVENT_VENC_CMDQ_MB_DONE              
120 #define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE     
121 #define CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_D    
122 #define CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_D    
123 #define CMDQ_EVENT_VENC_CMDQ_PPS_DONE             
124 #define CMDQ_EVENT_VENC_CMDQ_SPS_DONE             
125 #define CMDQ_EVENT_VENC_CMDQ_VPS_DONE             
126                                                   
127 #define CMDQ_EVENT_VDEC_CORE0_SOF_0               
128 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0        
129 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1        
130 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2        
131 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3        
132 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4        
133 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5        
134 #define CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6        
135 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0         
136 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1         
137 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2         
138 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3         
139 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_4         
140 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_5         
141 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_6         
142 #define CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7         
143 #define CMDQ_EVENT_FDVT_DONE                      
144 #define CMDQ_EVENT_FE_DONE                        
145 #define CMDQ_EVENT_RSC_DONE                       
146 #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT            
147 #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT            
148                                                   
149 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0       
150 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1       
151 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2       
152 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3       
153 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4       
154 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5       
155 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6       
156 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7       
157 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8       
158 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9       
159 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10      
160 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11      
161 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12      
162 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13      
163 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14      
164 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_15      
165 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_16      
166 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_17      
167 #define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_18      
168 #define CMDQ_EVENT_IMG2_DIP_DMA_ERR_EVENT         
169 #define CMDQ_EVENT_IMG2_AMD_FRAME_DONE            
170 #define CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC        
171 #define CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC      
172 #define CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC        
173                                                   
174 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0       
175 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1       
176 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2       
177 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3       
178 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4       
179 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5       
180 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6       
181 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7       
182 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8       
183 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9       
184 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10      
185 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11      
186 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12      
187 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13      
188 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14      
189 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15      
190 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16      
191 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17      
192 #define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18      
193 #define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT         
194 #define CMDQ_EVENT_IMG1_AMD_FRAME_DONE            
195 #define CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC        
196 #define CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC      
197 #define CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC        
198                                                   
199 #define CMDQ_EVENT_MDP_RDMA0_SOF                  
200 #define CMDQ_EVENT_MDP_RDMA1_SOF                  
201 #define CMDQ_EVENT_MDP_AAL0_SOF                   
202 #define CMDQ_EVENT_MDP_AAL1_SOF                   
203 #define CMDQ_EVENT_MDP_HDR0_SOF                   
204 #define CMDQ_EVENT_MDP_HDR1_SOF                   
205 #define CMDQ_EVENT_MDP_RSZ0_SOF                   
206 #define CMDQ_EVENT_MDP_RSZ1_SOF                   
207 #define CMDQ_EVENT_MDP_WROT0_SOF                  
208 #define CMDQ_EVENT_MDP_WROT1_SOF                  
209 #define CMDQ_EVENT_MDP_TDSHP0_SOF                 
210 #define CMDQ_EVENT_MDP_TDSHP1_SOF                 
211 #define CMDQ_EVENT_IMG_DL_RELAY0_SOF              
212 #define CMDQ_EVENT_IMG_DL_RELAY1_SOF              
213 #define CMDQ_EVENT_MDP_COLOR0_SOF                 
214 #define CMDQ_EVENT_MDP_COLOR1_SOF                 
215 #define CMDQ_EVENT_MDP_WROT1_FRAME_DONE           
216 #define CMDQ_EVENT_MDP_WROT0_FRAME_DONE           
217 #define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE          
218 #define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE          
219 #define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE            
220 #define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE            
221 #define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE           
222 #define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE           
223 #define CMDQ_EVENT_MDP_HDR1_FRAME_DONE            
224 #define CMDQ_EVENT_MDP_HDR0_FRAME_DONE            
225 #define CMDQ_EVENT_MDP_COLOR1_FRAME_DONE          
226 #define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE          
227 #define CMDQ_EVENT_MDP_AAL1_FRAME_DONE            
228 #define CMDQ_EVENT_MDP_AAL0_FRAME_DONE            
229 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0    
230 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
231 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2    
232 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3    
233 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4    
234 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5    
235 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6    
236 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7    
237 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8    
238 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9    
239 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
240 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
241 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
242 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
243 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
244 #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1    
245 #define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_E    
246 #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_E    
247 #define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_E    
248 #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_E    
249                                                   
250 #define CMDQ_EVENT_DISP_OVL0_SOF                  
251 #define CMDQ_EVENT_DISP_OVL0_2L_SOF               
252 #define CMDQ_EVENT_DISP_RDMA0_SOF                 
253 #define CMDQ_EVENT_DISP_RSZ0_SOF                  
254 #define CMDQ_EVENT_DISP_COLOR0_SOF                
255 #define CMDQ_EVENT_DISP_CCORR0_SOF                
256 #define CMDQ_EVENT_DISP_AAL0_SOF                  
257 #define CMDQ_EVENT_DISP_GAMMA0_SOF                
258 #define CMDQ_EVENT_DISP_POSTMASK0_SOF             
259 #define CMDQ_EVENT_DISP_DITHER0_SOF               
260 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_SOF       
261 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_SOF       
262 #define CMDQ_EVENT_DSI0_SOF                       
263 #define CMDQ_EVENT_DISP_WDMA0_SOF                 
264 #define CMDQ_EVENT_DISP_UFBC_WDMA0_SOF            
265 #define CMDQ_EVENT_DISP_PWM0_SOF                  
266 #define CMDQ_EVENT_DISP_OVL2_2L_SOF               
267 #define CMDQ_EVENT_DISP_RDMA4_SOF                 
268 #define CMDQ_EVENT_DISP_DPI0_SOF                  
269 #define CMDQ_EVENT_MDP_RDMA4_SOF                  
270 #define CMDQ_EVENT_MDP_HDR4_SOF                   
271 #define CMDQ_EVENT_MDP_RSZ4_SOF                   
272 #define CMDQ_EVENT_MDP_AAL4_SOF                   
273 #define CMDQ_EVENT_MDP_TDSHP4_SOF                 
274 #define CMDQ_EVENT_MDP_COLOR4_SOF                 
275 #define CMDQ_EVENT_DISP_Y2R0_SOF                  
276 #define CMDQ_EVENT_MDP_TDSHP4_FRAME_DONE          
277 #define CMDQ_EVENT_MDP_RSZ4_FRAME_DONE            
278 #define CMDQ_EVENT_MDP_RDMA4_FRAME_DONE           
279 #define CMDQ_EVENT_MDP_HDR4_FRAME_DONE            
280 #define CMDQ_EVENT_MDP_COLOR4_FRAME_DONE          
281 #define CMDQ_EVENT_MDP_AAL4_FRAME_DONE            
282 #define CMDQ_EVENT_DSI0_FRAME_DONE                
283 #define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE          
284 #define CMDQ_EVENT_DISP_UFBC_WDMA0_FRAME_DONE     
285 #define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE           
286 #define CMDQ_EVENT_DISP_RDMA4_FRAME_DONE          
287 #define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE          
288 #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE      
289 #define CMDQ_EVENT_DISP_OVL2_2L_FRAME_DONE        
290 #define CMDQ_EVENT_DISP_OVL0_FRAME_DONE           
291 #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE        
292 #define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE         
293 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE1_FRAME_    
294 #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_    
295 #define CMDQ_EVENT_DISP_DPI0_FRAME_DONE           
296 #define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE        
297 #define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE         
298 #define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE         
299 #define CMDQ_EVENT_DISP_AAL0_FRAME_DONE           
300 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
301 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
302 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
303 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
304 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
305 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
306 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
307 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
308 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
309 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
310 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
311 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
312 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
313 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
314 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
315 #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_    
316 #define CMDQ_EVENT_DSI0_TE_ENG_EVENT              
317 #define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT             
318 #define CMDQ_EVENT_DSI0_DONE_ENG_EVENT            
319 #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_    
320 #define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT       
321 #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG    
322 #define CMDQ_EVENT_DISP_OVL2_2L_RST_DONE_ENG_E    
323 #define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVEN    
324 #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_E    
325 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0       
326 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1       
327 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2       
328 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3       
329 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4       
330 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5       
331 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6       
332 #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7       
333 #define CMDQ_MAX_HW_EVENT                         
334                                                   
335 #endif                                            
336                                                   

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