1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2- 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Cen 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 4 */ 5 5 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_ 6 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_ 7 #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 8 8 9 #define MASTER_QPIC_CORE 0 9 #define MASTER_QPIC_CORE 0 10 #define MASTER_QUP_CORE_0 1 10 #define MASTER_QUP_CORE_0 1 11 #define SLAVE_QPIC_CORE 2 11 #define SLAVE_QPIC_CORE 2 12 #define SLAVE_QUP_CORE_0 3 12 #define SLAVE_QUP_CORE_0 3 13 13 14 #define MASTER_LLCC 0 14 #define MASTER_LLCC 0 15 #define SLAVE_EBI1 1 15 #define SLAVE_EBI1 1 16 16 17 #define MASTER_CNOC_DC_NOC 0 17 #define MASTER_CNOC_DC_NOC 0 18 #define SLAVE_LAGG_CFG 1 18 #define SLAVE_LAGG_CFG 1 19 #define SLAVE_MCCC_MASTER 2 19 #define SLAVE_MCCC_MASTER 2 20 #define SLAVE_GEM_NOC_CFG 3 20 #define SLAVE_GEM_NOC_CFG 3 21 #define SLAVE_SNOOP_BWMON 4 21 #define SLAVE_SNOOP_BWMON 4 22 22 23 #define MASTER_SYS_TCU 0 23 #define MASTER_SYS_TCU 0 24 #define MASTER_APPSS_PROC 1 24 #define MASTER_APPSS_PROC 1 25 #define MASTER_GEM_NOC_CFG 2 25 #define MASTER_GEM_NOC_CFG 2 26 #define MASTER_MSS_PROC 3 26 #define MASTER_MSS_PROC 3 27 #define MASTER_ANOC_PCIE_GEM_NOC 4 27 #define MASTER_ANOC_PCIE_GEM_NOC 4 28 #define MASTER_SNOC_SF_MEM_NOC 5 28 #define MASTER_SNOC_SF_MEM_NOC 5 29 #define MASTER_GIC 6 29 #define MASTER_GIC 6 30 #define MASTER_IPA_PCIE 7 30 #define MASTER_IPA_PCIE 7 31 #define SLAVE_GEM_NOC_CNOC 8 31 #define SLAVE_GEM_NOC_CNOC 8 32 #define SLAVE_LLCC 9 32 #define SLAVE_LLCC 9 33 #define SLAVE_MEM_NOC_PCIE_SNOC 10 33 #define SLAVE_MEM_NOC_PCIE_SNOC 10 34 #define SLAVE_SERVICE_GEM_NOC 11 34 #define SLAVE_SERVICE_GEM_NOC 11 35 35 36 #define MASTER_PCIE_0 0 36 #define MASTER_PCIE_0 0 37 #define MASTER_PCIE_1 1 37 #define MASTER_PCIE_1 1 38 #define MASTER_PCIE_2 2 38 #define MASTER_PCIE_2 2 39 #define SLAVE_ANOC_PCIE_GEM_NOC 3 39 #define SLAVE_ANOC_PCIE_GEM_NOC 3 40 40 41 #define MASTER_AUDIO 0 41 #define MASTER_AUDIO 0 42 #define MASTER_GIC_AHB 1 42 #define MASTER_GIC_AHB 1 43 #define MASTER_PCIE_RSCC 2 43 #define MASTER_PCIE_RSCC 2 44 #define MASTER_QDSS_BAM 3 44 #define MASTER_QDSS_BAM 3 45 #define MASTER_QPIC 4 45 #define MASTER_QPIC 4 46 #define MASTER_QUP_0 5 46 #define MASTER_QUP_0 5 47 #define MASTER_ANOC_SNOC 6 47 #define MASTER_ANOC_SNOC 6 48 #define MASTER_GEM_NOC_CNOC 7 48 #define MASTER_GEM_NOC_CNOC 7 49 #define MASTER_GEM_NOC_PCIE_SNOC 8 49 #define MASTER_GEM_NOC_PCIE_SNOC 8 50 #define MASTER_SNOC_CFG 9 50 #define MASTER_SNOC_CFG 9 51 #define MASTER_PCIE_ANOC_CFG 10 51 #define MASTER_PCIE_ANOC_CFG 10 52 #define MASTER_CRYPTO 11 52 #define MASTER_CRYPTO 11 53 #define MASTER_IPA 12 53 #define MASTER_IPA 12 54 #define MASTER_MVMSS 13 54 #define MASTER_MVMSS 13 55 #define MASTER_EMAC_0 14 55 #define MASTER_EMAC_0 14 56 #define MASTER_EMAC_1 15 56 #define MASTER_EMAC_1 15 57 #define MASTER_QDSS_ETR 16 57 #define MASTER_QDSS_ETR 16 58 #define MASTER_QDSS_ETR_1 17 58 #define MASTER_QDSS_ETR_1 17 59 #define MASTER_SDCC_1 18 59 #define MASTER_SDCC_1 18 60 #define MASTER_SDCC_4 19 60 #define MASTER_SDCC_4 19 61 #define MASTER_USB3_0 20 61 #define MASTER_USB3_0 20 62 #define SLAVE_ETH0_CFG 21 62 #define SLAVE_ETH0_CFG 21 63 #define SLAVE_ETH1_CFG 22 63 #define SLAVE_ETH1_CFG 22 64 #define SLAVE_AUDIO 23 64 #define SLAVE_AUDIO 23 65 #define SLAVE_CLK_CTL 24 65 #define SLAVE_CLK_CTL 24 66 #define SLAVE_CRYPTO_0_CFG 25 66 #define SLAVE_CRYPTO_0_CFG 25 67 #define SLAVE_IMEM_CFG 26 67 #define SLAVE_IMEM_CFG 26 68 #define SLAVE_IPA_CFG 27 68 #define SLAVE_IPA_CFG 27 69 #define SLAVE_IPC_ROUTER_CFG 28 69 #define SLAVE_IPC_ROUTER_CFG 28 70 #define SLAVE_CNOC_MSS 29 70 #define SLAVE_CNOC_MSS 29 71 #define SLAVE_ICBDI_MVMSS_CFG 30 71 #define SLAVE_ICBDI_MVMSS_CFG 30 72 #define SLAVE_PCIE_0_CFG 31 72 #define SLAVE_PCIE_0_CFG 31 73 #define SLAVE_PCIE_1_CFG 32 73 #define SLAVE_PCIE_1_CFG 32 74 #define SLAVE_PCIE_2_CFG 33 74 #define SLAVE_PCIE_2_CFG 33 75 #define SLAVE_PCIE_RSC_CFG 34 75 #define SLAVE_PCIE_RSC_CFG 34 76 #define SLAVE_PDM 35 76 #define SLAVE_PDM 35 77 #define SLAVE_PRNG 36 77 #define SLAVE_PRNG 36 78 #define SLAVE_QDSS_CFG 37 78 #define SLAVE_QDSS_CFG 37 79 #define SLAVE_QPIC 38 79 #define SLAVE_QPIC 38 80 #define SLAVE_QUP_0 39 80 #define SLAVE_QUP_0 39 81 #define SLAVE_SDCC_1 40 81 #define SLAVE_SDCC_1 40 82 #define SLAVE_SDCC_4 41 82 #define SLAVE_SDCC_4 41 83 #define SLAVE_SPMI_VGI_COEX 42 83 #define SLAVE_SPMI_VGI_COEX 42 84 #define SLAVE_TCSR 43 84 #define SLAVE_TCSR 43 85 #define SLAVE_TLMM 44 85 #define SLAVE_TLMM 44 86 #define SLAVE_USB3 45 86 #define SLAVE_USB3 45 87 #define SLAVE_USB3_PHY_CFG 46 87 #define SLAVE_USB3_PHY_CFG 46 88 #define SLAVE_A1NOC_CFG 47 88 #define SLAVE_A1NOC_CFG 47 89 #define SLAVE_DDRSS_CFG 48 89 #define SLAVE_DDRSS_CFG 48 90 #define SLAVE_SNOC_GEM_NOC_SF 49 90 #define SLAVE_SNOC_GEM_NOC_SF 49 91 #define SLAVE_SNOC_CFG 50 91 #define SLAVE_SNOC_CFG 50 92 #define SLAVE_PCIE_ANOC_CFG 51 92 #define SLAVE_PCIE_ANOC_CFG 51 93 #define SLAVE_IMEM 52 93 #define SLAVE_IMEM 52 94 #define SLAVE_SERVICE_PCIE_ANOC 53 94 #define SLAVE_SERVICE_PCIE_ANOC 53 95 #define SLAVE_SERVICE_SNOC 54 95 #define SLAVE_SERVICE_SNOC 54 96 #define SLAVE_PCIE_0 55 96 #define SLAVE_PCIE_0 55 97 #define SLAVE_PCIE_1 56 97 #define SLAVE_PCIE_1 56 98 #define SLAVE_PCIE_2 57 98 #define SLAVE_PCIE_2 57 99 #define SLAVE_QDSS_STM 58 99 #define SLAVE_QDSS_STM 58 100 #define SLAVE_TCU 59 100 #define SLAVE_TCU 59 101 101 102 #endif 102 #endif 103 103
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