1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * Xilinx Video IP Core 3 * Xilinx Video IP Core 4 * 4 * 5 * Copyright (C) 2013-2015 Ideas on Board 5 * Copyright (C) 2013-2015 Ideas on Board 6 * Copyright (C) 2013-2015 Xilinx, Inc. 6 * Copyright (C) 2013-2015 Xilinx, Inc. 7 * 7 * 8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9 * Laurent Pinchart <laurent.pinchar 9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 10 */ 11 11 12 #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 12 #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 13 #define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 13 #define __DT_BINDINGS_MEDIA_XILINX_VIP_H__ 14 14 15 /* 15 /* 16 * Video format codes as defined in "AXI4-Stre 16 * Video format codes as defined in "AXI4-Stream Video IP and System Design 17 * Guide". 17 * Guide". 18 */ 18 */ 19 #define XVIP_VF_YUV_422 0 19 #define XVIP_VF_YUV_422 0 20 #define XVIP_VF_YUV_444 1 20 #define XVIP_VF_YUV_444 1 21 #define XVIP_VF_RBG 2 21 #define XVIP_VF_RBG 2 22 #define XVIP_VF_YUV_420 3 22 #define XVIP_VF_YUV_420 3 23 #define XVIP_VF_YUVA_422 4 23 #define XVIP_VF_YUVA_422 4 24 #define XVIP_VF_YUVA_444 5 24 #define XVIP_VF_YUVA_444 5 25 #define XVIP_VF_RGBA 6 25 #define XVIP_VF_RGBA 6 26 #define XVIP_VF_YUVA_420 7 26 #define XVIP_VF_YUVA_420 7 27 #define XVIP_VF_YUVD_422 8 27 #define XVIP_VF_YUVD_422 8 28 #define XVIP_VF_YUVD_444 9 28 #define XVIP_VF_YUVD_444 9 29 #define XVIP_VF_RGBD 10 29 #define XVIP_VF_RGBD 10 30 #define XVIP_VF_YUVD_420 11 30 #define XVIP_VF_YUVD_420 11 31 #define XVIP_VF_MONO_SENSOR 12 31 #define XVIP_VF_MONO_SENSOR 12 32 #define XVIP_VF_CUSTOM2 13 32 #define XVIP_VF_CUSTOM2 13 33 #define XVIP_VF_CUSTOM3 14 33 #define XVIP_VF_CUSTOM3 14 34 #define XVIP_VF_CUSTOM4 15 34 #define XVIP_VF_CUSTOM4 15 35 35 36 #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ * 36 #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ 37 37
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