1 #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 1 #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 2 #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 2 #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 3 3 4 /* special clients */ 4 /* special clients */ 5 #define TEGRA186_SID_INVALID 0x00 5 #define TEGRA186_SID_INVALID 0x00 6 #define TEGRA186_SID_PASSTHROUGH 0x7f 6 #define TEGRA186_SID_PASSTHROUGH 0x7f 7 7 8 /* host1x clients */ 8 /* host1x clients */ 9 #define TEGRA186_SID_HOST1X 0x01 9 #define TEGRA186_SID_HOST1X 0x01 10 #define TEGRA186_SID_CSI 0x02 10 #define TEGRA186_SID_CSI 0x02 11 #define TEGRA186_SID_VIC 0x03 11 #define TEGRA186_SID_VIC 0x03 12 #define TEGRA186_SID_VI 0x04 12 #define TEGRA186_SID_VI 0x04 13 #define TEGRA186_SID_ISP 0x05 13 #define TEGRA186_SID_ISP 0x05 14 #define TEGRA186_SID_NVDEC 0x06 14 #define TEGRA186_SID_NVDEC 0x06 15 #define TEGRA186_SID_NVENC 0x07 15 #define TEGRA186_SID_NVENC 0x07 16 #define TEGRA186_SID_NVJPG 0x08 16 #define TEGRA186_SID_NVJPG 0x08 17 #define TEGRA186_SID_NVDISPLAY 0x09 17 #define TEGRA186_SID_NVDISPLAY 0x09 18 #define TEGRA186_SID_TSEC 0x0a 18 #define TEGRA186_SID_TSEC 0x0a 19 #define TEGRA186_SID_TSECB 0x0b 19 #define TEGRA186_SID_TSECB 0x0b 20 #define TEGRA186_SID_SE 0x0c 20 #define TEGRA186_SID_SE 0x0c 21 #define TEGRA186_SID_SE1 0x0d 21 #define TEGRA186_SID_SE1 0x0d 22 #define TEGRA186_SID_SE2 0x0e 22 #define TEGRA186_SID_SE2 0x0e 23 #define TEGRA186_SID_SE3 0x0f 23 #define TEGRA186_SID_SE3 0x0f 24 24 25 /* GPU clients */ 25 /* GPU clients */ 26 #define TEGRA186_SID_GPU 0x10 26 #define TEGRA186_SID_GPU 0x10 27 27 28 /* other SoC clients */ 28 /* other SoC clients */ 29 #define TEGRA186_SID_AFI 0x11 29 #define TEGRA186_SID_AFI 0x11 30 #define TEGRA186_SID_HDA 0x12 30 #define TEGRA186_SID_HDA 0x12 31 #define TEGRA186_SID_ETR 0x13 31 #define TEGRA186_SID_ETR 0x13 32 #define TEGRA186_SID_EQOS 0x14 32 #define TEGRA186_SID_EQOS 0x14 33 #define TEGRA186_SID_UFSHC 0x15 33 #define TEGRA186_SID_UFSHC 0x15 34 #define TEGRA186_SID_AON 0x16 34 #define TEGRA186_SID_AON 0x16 35 #define TEGRA186_SID_SDMMC4 0x17 35 #define TEGRA186_SID_SDMMC4 0x17 36 #define TEGRA186_SID_SDMMC3 0x18 36 #define TEGRA186_SID_SDMMC3 0x18 37 #define TEGRA186_SID_SDMMC2 0x19 37 #define TEGRA186_SID_SDMMC2 0x19 38 #define TEGRA186_SID_SDMMC1 0x1a 38 #define TEGRA186_SID_SDMMC1 0x1a 39 #define TEGRA186_SID_XUSB_HOST 0x1b 39 #define TEGRA186_SID_XUSB_HOST 0x1b 40 #define TEGRA186_SID_XUSB_DEV 0x1c 40 #define TEGRA186_SID_XUSB_DEV 0x1c 41 #define TEGRA186_SID_SATA 0x1d 41 #define TEGRA186_SID_SATA 0x1d 42 #define TEGRA186_SID_APE 0x1e 42 #define TEGRA186_SID_APE 0x1e 43 #define TEGRA186_SID_SCE 0x1f 43 #define TEGRA186_SID_SCE 0x1f 44 44 45 /* GPC DMA clients */ 45 /* GPC DMA clients */ 46 #define TEGRA186_SID_GPCDMA_0 0x20 46 #define TEGRA186_SID_GPCDMA_0 0x20 47 #define TEGRA186_SID_GPCDMA_1 0x21 47 #define TEGRA186_SID_GPCDMA_1 0x21 48 #define TEGRA186_SID_GPCDMA_2 0x22 48 #define TEGRA186_SID_GPCDMA_2 0x22 49 #define TEGRA186_SID_GPCDMA_3 0x23 49 #define TEGRA186_SID_GPCDMA_3 0x23 50 #define TEGRA186_SID_GPCDMA_4 0x24 50 #define TEGRA186_SID_GPCDMA_4 0x24 51 #define TEGRA186_SID_GPCDMA_5 0x25 51 #define TEGRA186_SID_GPCDMA_5 0x25 52 #define TEGRA186_SID_GPCDMA_6 0x26 52 #define TEGRA186_SID_GPCDMA_6 0x26 53 #define TEGRA186_SID_GPCDMA_7 0x27 53 #define TEGRA186_SID_GPCDMA_7 0x27 54 54 55 /* APE DMA clients */ 55 /* APE DMA clients */ 56 #define TEGRA186_SID_APE_1 0x28 56 #define TEGRA186_SID_APE_1 0x28 57 #define TEGRA186_SID_APE_2 0x29 57 #define TEGRA186_SID_APE_2 0x29 58 58 59 /* camera RTCPU */ 59 /* camera RTCPU */ 60 #define TEGRA186_SID_RCE 0x2a 60 #define TEGRA186_SID_RCE 0x2a 61 61 62 /* camera RTCPU on host1x address space */ 62 /* camera RTCPU on host1x address space */ 63 #define TEGRA186_SID_RCE_1X 0x2b 63 #define TEGRA186_SID_RCE_1X 0x2b 64 64 65 /* APE DMA clients */ 65 /* APE DMA clients */ 66 #define TEGRA186_SID_APE_3 0x2c 66 #define TEGRA186_SID_APE_3 0x2c 67 67 68 /* camera RTCPU running on APE */ 68 /* camera RTCPU running on APE */ 69 #define TEGRA186_SID_APE_CAM 0x2d 69 #define TEGRA186_SID_APE_CAM 0x2d 70 #define TEGRA186_SID_APE_CAM_1X 0x2e 70 #define TEGRA186_SID_APE_CAM_1X 0x2e 71 71 72 /* 72 /* 73 * The BPMP has its SID value hardcoded in the 73 * The BPMP has its SID value hardcoded in the firmware. Changing it requires 74 * considerable effort. 74 * considerable effort. 75 */ 75 */ 76 #define TEGRA186_SID_BPMP 0x32 76 #define TEGRA186_SID_BPMP 0x32 77 77 78 /* for SMMU tests */ 78 /* for SMMU tests */ 79 #define TEGRA186_SID_SMMU_TEST 0x33 79 #define TEGRA186_SID_SMMU_TEST 0x33 80 80 81 /* host1x virtualization channels */ 81 /* host1x virtualization channels */ 82 #define TEGRA186_SID_HOST1X_CTX0 0x38 82 #define TEGRA186_SID_HOST1X_CTX0 0x38 83 #define TEGRA186_SID_HOST1X_CTX1 0x39 83 #define TEGRA186_SID_HOST1X_CTX1 0x39 84 #define TEGRA186_SID_HOST1X_CTX2 0x3a 84 #define TEGRA186_SID_HOST1X_CTX2 0x3a 85 #define TEGRA186_SID_HOST1X_CTX3 0x3b 85 #define TEGRA186_SID_HOST1X_CTX3 0x3b 86 #define TEGRA186_SID_HOST1X_CTX4 0x3c 86 #define TEGRA186_SID_HOST1X_CTX4 0x3c 87 #define TEGRA186_SID_HOST1X_CTX5 0x3d 87 #define TEGRA186_SID_HOST1X_CTX5 0x3d 88 #define TEGRA186_SID_HOST1X_CTX6 0x3e 88 #define TEGRA186_SID_HOST1X_CTX6 0x3e 89 #define TEGRA186_SID_HOST1X_CTX7 0x3f 89 #define TEGRA186_SID_HOST1X_CTX7 0x3f 90 90 91 /* host1x command buffers */ 91 /* host1x command buffers */ 92 #define TEGRA186_SID_HOST1X_VM0 0x40 92 #define TEGRA186_SID_HOST1X_VM0 0x40 93 #define TEGRA186_SID_HOST1X_VM1 0x41 93 #define TEGRA186_SID_HOST1X_VM1 0x41 94 #define TEGRA186_SID_HOST1X_VM2 0x42 94 #define TEGRA186_SID_HOST1X_VM2 0x42 95 #define TEGRA186_SID_HOST1X_VM3 0x43 95 #define TEGRA186_SID_HOST1X_VM3 0x43 96 #define TEGRA186_SID_HOST1X_VM4 0x44 96 #define TEGRA186_SID_HOST1X_VM4 0x44 97 #define TEGRA186_SID_HOST1X_VM5 0x45 97 #define TEGRA186_SID_HOST1X_VM5 0x45 98 #define TEGRA186_SID_HOST1X_VM6 0x46 98 #define TEGRA186_SID_HOST1X_VM6 0x46 99 #define TEGRA186_SID_HOST1X_VM7 0x47 99 #define TEGRA186_SID_HOST1X_VM7 0x47 100 100 101 /* SE data buffers */ 101 /* SE data buffers */ 102 #define TEGRA186_SID_SE_VM0 0x48 102 #define TEGRA186_SID_SE_VM0 0x48 103 #define TEGRA186_SID_SE_VM1 0x49 103 #define TEGRA186_SID_SE_VM1 0x49 104 #define TEGRA186_SID_SE_VM2 0x4a 104 #define TEGRA186_SID_SE_VM2 0x4a 105 #define TEGRA186_SID_SE_VM3 0x4b 105 #define TEGRA186_SID_SE_VM3 0x4b 106 #define TEGRA186_SID_SE_VM4 0x4c 106 #define TEGRA186_SID_SE_VM4 0x4c 107 #define TEGRA186_SID_SE_VM5 0x4d 107 #define TEGRA186_SID_SE_VM5 0x4d 108 #define TEGRA186_SID_SE_VM6 0x4e 108 #define TEGRA186_SID_SE_VM6 0x4e 109 #define TEGRA186_SID_SE_VM7 0x4f 109 #define TEGRA186_SID_SE_VM7 0x4f 110 110 111 /* 111 /* 112 * memory client IDs 112 * memory client IDs 113 */ 113 */ 114 114 115 /* Misses from System Memory Management Unit ( 115 /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 116 #define TEGRA186_MEMORY_CLIENT_PTCR 0x00 116 #define TEGRA186_MEMORY_CLIENT_PTCR 0x00 117 /* PCIE reads */ 117 /* PCIE reads */ 118 #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e 118 #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e 119 /* High-definition audio (HDA) reads */ 119 /* High-definition audio (HDA) reads */ 120 #define TEGRA186_MEMORY_CLIENT_HDAR 0x15 120 #define TEGRA186_MEMORY_CLIENT_HDAR 0x15 121 /* Host channel data reads */ 121 /* Host channel data reads */ 122 #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 122 #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 123 #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c 123 #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c 124 /* SATA reads */ 124 /* SATA reads */ 125 #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f 125 #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f 126 /* Reads from Cortex-A9 4 CPU cores via the L2 126 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 127 #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 127 #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 128 #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b 128 #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b 129 /* PCIE writes */ 129 /* PCIE writes */ 130 #define TEGRA186_MEMORY_CLIENT_AFIW 0x31 130 #define TEGRA186_MEMORY_CLIENT_AFIW 0x31 131 /* High-definition audio (HDA) writes */ 131 /* High-definition audio (HDA) writes */ 132 #define TEGRA186_MEMORY_CLIENT_HDAW 0x35 132 #define TEGRA186_MEMORY_CLIENT_HDAW 0x35 133 /* Writes from Cortex-A9 4 CPU cores via the L 133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 134 #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 134 #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 135 /* SATA writes */ 135 /* SATA writes */ 136 #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d 136 #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d 137 /* ISP Read client for Crossbar A */ 137 /* ISP Read client for Crossbar A */ 138 #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 138 #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 139 /* ISP Write client for Crossbar A */ 139 /* ISP Write client for Crossbar A */ 140 #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 140 #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 141 /* ISP Write client Crossbar B */ 141 /* ISP Write client Crossbar B */ 142 #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 142 #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 143 /* XUSB reads */ 143 /* XUSB reads */ 144 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a 144 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a 145 /* XUSB_HOST writes */ 145 /* XUSB_HOST writes */ 146 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b 146 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b 147 /* XUSB reads */ 147 /* XUSB reads */ 148 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c 148 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c 149 /* XUSB_DEV writes */ 149 /* XUSB_DEV writes */ 150 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d 150 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d 151 /* TSEC Memory Return Data Client Description 151 /* TSEC Memory Return Data Client Description */ 152 #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 152 #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 153 /* TSEC Memory Write Client Description */ 153 /* TSEC Memory Write Client Description */ 154 #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 154 #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 155 /* 3D, ltcx reads instance 0 */ 155 /* 3D, ltcx reads instance 0 */ 156 #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 156 #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 157 /* 3D, ltcx writes instance 0 */ 157 /* 3D, ltcx writes instance 0 */ 158 #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 158 #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 159 /* sdmmca memory read client */ 159 /* sdmmca memory read client */ 160 #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 160 #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 161 /* sdmmcbmemory read client */ 161 /* sdmmcbmemory read client */ 162 #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 162 #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 163 /* sdmmc memory read client */ 163 /* sdmmc memory read client */ 164 #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 164 #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 165 /* sdmmcd memory read client */ 165 /* sdmmcd memory read client */ 166 #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 166 #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 167 /* sdmmca memory write client */ 167 /* sdmmca memory write client */ 168 #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 168 #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 169 /* sdmmcb memory write client */ 169 /* sdmmcb memory write client */ 170 #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 170 #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 171 /* sdmmc memory write client */ 171 /* sdmmc memory write client */ 172 #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 172 #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 173 /* sdmmcd memory write client */ 173 /* sdmmcd memory write client */ 174 #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 174 #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 175 #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c 175 #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c 176 #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d 176 #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d 177 /* VI Write client */ 177 /* VI Write client */ 178 #define TEGRA186_MEMORY_CLIENT_VIW 0x72 178 #define TEGRA186_MEMORY_CLIENT_VIW 0x72 179 #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 179 #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 180 #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 180 #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 181 /* Audio Processing (APE) engine reads */ 181 /* Audio Processing (APE) engine reads */ 182 #define TEGRA186_MEMORY_CLIENT_APER 0x7a 182 #define TEGRA186_MEMORY_CLIENT_APER 0x7a 183 /* Audio Processing (APE) engine writes */ 183 /* Audio Processing (APE) engine writes */ 184 #define TEGRA186_MEMORY_CLIENT_APEW 0x7b 184 #define TEGRA186_MEMORY_CLIENT_APEW 0x7b 185 #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e 185 #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e 186 #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f 186 #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f 187 /* SE Memory Return Data Client Description */ 187 /* SE Memory Return Data Client Description */ 188 #define TEGRA186_MEMORY_CLIENT_SESRD 0x80 188 #define TEGRA186_MEMORY_CLIENT_SESRD 0x80 189 /* SE Memory Write Client Description */ 189 /* SE Memory Write Client Description */ 190 #define TEGRA186_MEMORY_CLIENT_SESWR 0x81 190 #define TEGRA186_MEMORY_CLIENT_SESWR 0x81 191 /* ETR reads */ 191 /* ETR reads */ 192 #define TEGRA186_MEMORY_CLIENT_ETRR 0x84 192 #define TEGRA186_MEMORY_CLIENT_ETRR 0x84 193 /* ETR writes */ 193 /* ETR writes */ 194 #define TEGRA186_MEMORY_CLIENT_ETRW 0x85 194 #define TEGRA186_MEMORY_CLIENT_ETRW 0x85 195 /* TSECB Memory Return Data Client Description 195 /* TSECB Memory Return Data Client Description */ 196 #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 196 #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 197 /* TSECB Memory Write Client Description */ 197 /* TSECB Memory Write Client Description */ 198 #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 198 #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 199 /* 3D, ltcx reads instance 1 */ 199 /* 3D, ltcx reads instance 1 */ 200 #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 200 #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 201 /* 3D, ltcx writes instance 1 */ 201 /* 3D, ltcx writes instance 1 */ 202 #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 202 #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 203 /* AXI Switch read client */ 203 /* AXI Switch read client */ 204 #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c 204 #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c 205 /* AXI Switch write client */ 205 /* AXI Switch write client */ 206 #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d 206 #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d 207 /* EQOS read client */ 207 /* EQOS read client */ 208 #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e 208 #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e 209 /* EQOS write client */ 209 /* EQOS write client */ 210 #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f 210 #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f 211 /* UFSHC read client */ 211 /* UFSHC read client */ 212 #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 212 #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 213 /* UFSHC write client */ 213 /* UFSHC write client */ 214 #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 214 #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 215 /* NVDISPLAY read client */ 215 /* NVDISPLAY read client */ 216 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 216 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 217 /* BPMP read client */ 217 /* BPMP read client */ 218 #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 218 #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 219 /* BPMP write client */ 219 /* BPMP write client */ 220 #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 220 #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 221 /* BPMPDMA read client */ 221 /* BPMPDMA read client */ 222 #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 222 #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 223 /* BPMPDMA write client */ 223 /* BPMPDMA write client */ 224 #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 224 #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 225 /* AON read client */ 225 /* AON read client */ 226 #define TEGRA186_MEMORY_CLIENT_AONR 0x97 226 #define TEGRA186_MEMORY_CLIENT_AONR 0x97 227 /* AON write client */ 227 /* AON write client */ 228 #define TEGRA186_MEMORY_CLIENT_AONW 0x98 228 #define TEGRA186_MEMORY_CLIENT_AONW 0x98 229 /* AONDMA read client */ 229 /* AONDMA read client */ 230 #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 230 #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 231 /* AONDMA write client */ 231 /* AONDMA write client */ 232 #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a 232 #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a 233 /* SCE read client */ 233 /* SCE read client */ 234 #define TEGRA186_MEMORY_CLIENT_SCER 0x9b 234 #define TEGRA186_MEMORY_CLIENT_SCER 0x9b 235 /* SCE write client */ 235 /* SCE write client */ 236 #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c 236 #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c 237 /* SCEDMA read client */ 237 /* SCEDMA read client */ 238 #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d 238 #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d 239 /* SCEDMA write client */ 239 /* SCEDMA write client */ 240 #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e 240 #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e 241 /* APEDMA read client */ 241 /* APEDMA read client */ 242 #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f 242 #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f 243 /* APEDMA write client */ 243 /* APEDMA write client */ 244 #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 244 #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 245 /* NVDISPLAY read client instance 2 */ 245 /* NVDISPLAY read client instance 2 */ 246 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa 246 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 247 #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 247 #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 248 #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 248 #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 249 249 250 #endif 250 #endif 251 251
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