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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/mfd/stm32h7-rcc.h

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Diff markup

Differences between /include/dt-bindings/mfd/stm32h7-rcc.h (Version linux-6.11.5) and /include/dt-bindings/mfd/stm32h7-rcc.h (Version linux-4.9.337)


  1 /*                                                  1 
  2  * This header provides constants for the STM3    
  3  */                                               
  4                                                   
  5 #ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H            
  6 #define _DT_BINDINGS_MFD_STM32H7_RCC_H            
  7                                                   
  8 /* AHB3 */                                        
  9 #define STM32H7_RCC_AHB3_MDMA           0         
 10 #define STM32H7_RCC_AHB3_DMA2D          4         
 11 #define STM32H7_RCC_AHB3_JPGDEC         5         
 12 #define STM32H7_RCC_AHB3_FMC            12        
 13 #define STM32H7_RCC_AHB3_QUADSPI        14        
 14 #define STM32H7_RCC_AHB3_SDMMC1         16        
 15 #define STM32H7_RCC_AHB3_CPU            31        
 16                                                   
 17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_A    
 18                                                   
 19 /* AHB1 */                                        
 20 #define STM32H7_RCC_AHB1_DMA1           0         
 21 #define STM32H7_RCC_AHB1_DMA2           1         
 22 #define STM32H7_RCC_AHB1_ADC12          5         
 23 #define STM32H7_RCC_AHB1_ART            14        
 24 #define STM32H7_RCC_AHB1_ETH1MAC        15        
 25 #define STM32H7_RCC_AHB1_USB1OTG        25        
 26 #define STM32H7_RCC_AHB1_USB2OTG        27        
 27                                                   
 28 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_A    
 29                                                   
 30 /* AHB2 */                                        
 31 #define STM32H7_RCC_AHB2_CAMITF         0         
 32 #define STM32H7_RCC_AHB2_CRYPT          4         
 33 #define STM32H7_RCC_AHB2_HASH           5         
 34 #define STM32H7_RCC_AHB2_RNG            6         
 35 #define STM32H7_RCC_AHB2_SDMMC2         9         
 36                                                   
 37 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_A    
 38                                                   
 39 /* AHB4 */                                        
 40 #define STM32H7_RCC_AHB4_GPIOA          0         
 41 #define STM32H7_RCC_AHB4_GPIOB          1         
 42 #define STM32H7_RCC_AHB4_GPIOC          2         
 43 #define STM32H7_RCC_AHB4_GPIOD          3         
 44 #define STM32H7_RCC_AHB4_GPIOE          4         
 45 #define STM32H7_RCC_AHB4_GPIOF          5         
 46 #define STM32H7_RCC_AHB4_GPIOG          6         
 47 #define STM32H7_RCC_AHB4_GPIOH          7         
 48 #define STM32H7_RCC_AHB4_GPIOI          8         
 49 #define STM32H7_RCC_AHB4_GPIOJ          9         
 50 #define STM32H7_RCC_AHB4_GPIOK          10        
 51 #define STM32H7_RCC_AHB4_CRC            19        
 52 #define STM32H7_RCC_AHB4_BDMA           21        
 53 #define STM32H7_RCC_AHB4_ADC3           24        
 54 #define STM32H7_RCC_AHB4_HSEM           25        
 55                                                   
 56 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_A    
 57                                                   
 58 /* APB3 */                                        
 59 #define STM32H7_RCC_APB3_LTDC           3         
 60 #define STM32H7_RCC_APB3_DSI            4         
 61                                                   
 62 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_A    
 63                                                   
 64 /* APB1L */                                       
 65 #define STM32H7_RCC_APB1L_TIM2          0         
 66 #define STM32H7_RCC_APB1L_TIM3          1         
 67 #define STM32H7_RCC_APB1L_TIM4          2         
 68 #define STM32H7_RCC_APB1L_TIM5          3         
 69 #define STM32H7_RCC_APB1L_TIM6          4         
 70 #define STM32H7_RCC_APB1L_TIM7          5         
 71 #define STM32H7_RCC_APB1L_TIM12         6         
 72 #define STM32H7_RCC_APB1L_TIM13         7         
 73 #define STM32H7_RCC_APB1L_TIM14         8         
 74 #define STM32H7_RCC_APB1L_LPTIM1        9         
 75 #define STM32H7_RCC_APB1L_SPI2          14        
 76 #define STM32H7_RCC_APB1L_SPI3          15        
 77 #define STM32H7_RCC_APB1L_SPDIF_RX      16        
 78 #define STM32H7_RCC_APB1L_USART2        17        
 79 #define STM32H7_RCC_APB1L_USART3        18        
 80 #define STM32H7_RCC_APB1L_UART4         19        
 81 #define STM32H7_RCC_APB1L_UART5         20        
 82 #define STM32H7_RCC_APB1L_I2C1          21        
 83 #define STM32H7_RCC_APB1L_I2C2          22        
 84 #define STM32H7_RCC_APB1L_I2C3          23        
 85 #define STM32H7_RCC_APB1L_HDMICEC       27        
 86 #define STM32H7_RCC_APB1L_DAC12         29        
 87 #define STM32H7_RCC_APB1L_USART7        30        
 88 #define STM32H7_RCC_APB1L_USART8        31        
 89                                                   
 90 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_    
 91                                                   
 92 /* APB1H */                                       
 93 #define STM32H7_RCC_APB1H_CRS           1         
 94 #define STM32H7_RCC_APB1H_SWP           2         
 95 #define STM32H7_RCC_APB1H_OPAMP         4         
 96 #define STM32H7_RCC_APB1H_MDIOS         5         
 97 #define STM32H7_RCC_APB1H_FDCAN         8         
 98                                                   
 99 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_    
100                                                   
101 /* APB2 */                                        
102 #define STM32H7_RCC_APB2_TIM1           0         
103 #define STM32H7_RCC_APB2_TIM8           1         
104 #define STM32H7_RCC_APB2_USART1         4         
105 #define STM32H7_RCC_APB2_USART6         5         
106 #define STM32H7_RCC_APB2_SPI1           12        
107 #define STM32H7_RCC_APB2_SPI4           13        
108 #define STM32H7_RCC_APB2_TIM15          16        
109 #define STM32H7_RCC_APB2_TIM16          17        
110 #define STM32H7_RCC_APB2_TIM17          18        
111 #define STM32H7_RCC_APB2_SPI5           20        
112 #define STM32H7_RCC_APB2_SAI1           22        
113 #define STM32H7_RCC_APB2_SAI2           23        
114 #define STM32H7_RCC_APB2_SAI3           24        
115 #define STM32H7_RCC_APB2_DFSDM1         28        
116 #define STM32H7_RCC_APB2_HRTIM          29        
117                                                   
118 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_A    
119                                                   
120 /* APB4 */                                        
121 #define STM32H7_RCC_APB4_SYSCFG         1         
122 #define STM32H7_RCC_APB4_LPUART1        3         
123 #define STM32H7_RCC_APB4_SPI6           5         
124 #define STM32H7_RCC_APB4_I2C4           7         
125 #define STM32H7_RCC_APB4_LPTIM2         9         
126 #define STM32H7_RCC_APB4_LPTIM3         10        
127 #define STM32H7_RCC_APB4_LPTIM4         11        
128 #define STM32H7_RCC_APB4_LPTIM5         12        
129 #define STM32H7_RCC_APB4_COMP12         14        
130 #define STM32H7_RCC_APB4_VREF           15        
131 #define STM32H7_RCC_APB4_SAI4           21        
132 #define STM32H7_RCC_APB4_TMPSENS        26        
133                                                   
134 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_A    
135                                                   
136 #endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */       
137                                                   

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