1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 2 /* 3 * This header provides constants for SERDES M 3 * This header provides constants for SERDES MUX for TI SoCs 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_MUX_TI_SERDES 6 #ifndef _DT_BINDINGS_MUX_TI_SERDES 7 #define _DT_BINDINGS_MUX_TI_SERDES 7 #define _DT_BINDINGS_MUX_TI_SERDES 8 8 9 /* << 10 * These bindings are deprecated, because they << 11 * concept of bindings but rather contain pure << 12 * in DTS board files. << 13 * Instead include the header in the DTS sourc << 14 */ << 15 #warning "These bindings are deprecated. Inste << 16 << 17 /* J721E */ 9 /* J721E */ 18 10 19 #define J721E_SERDES0_LANE0_QSGMII_LANE1 11 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 20 #define J721E_SERDES0_LANE0_PCIE0_LANE0 12 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 21 #define J721E_SERDES0_LANE0_USB3_0_SWAP 13 #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 22 #define J721E_SERDES0_LANE0_IP4_UNUSED 14 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 23 15 24 #define J721E_SERDES0_LANE1_QSGMII_LANE2 16 #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 25 #define J721E_SERDES0_LANE1_PCIE0_LANE1 17 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 26 #define J721E_SERDES0_LANE1_USB3_0 18 #define J721E_SERDES0_LANE1_USB3_0 0x2 27 #define J721E_SERDES0_LANE1_IP4_UNUSED 19 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 28 20 29 #define J721E_SERDES1_LANE0_QSGMII_LANE3 21 #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 30 #define J721E_SERDES1_LANE0_PCIE1_LANE0 22 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 31 #define J721E_SERDES1_LANE0_USB3_1_SWAP 23 #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 32 #define J721E_SERDES1_LANE0_SGMII_LANE0 24 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 33 25 34 #define J721E_SERDES1_LANE1_QSGMII_LANE4 26 #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 35 #define J721E_SERDES1_LANE1_PCIE1_LANE1 27 #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 36 #define J721E_SERDES1_LANE1_USB3_1 28 #define J721E_SERDES1_LANE1_USB3_1 0x2 37 #define J721E_SERDES1_LANE1_SGMII_LANE1 29 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 38 30 39 #define J721E_SERDES2_LANE0_IP1_UNUSED 31 #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 40 #define J721E_SERDES2_LANE0_PCIE2_LANE0 32 #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 41 #define J721E_SERDES2_LANE0_USB3_1_SWAP 33 #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 42 #define J721E_SERDES2_LANE0_SGMII_LANE0 34 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 43 35 44 #define J721E_SERDES2_LANE1_IP1_UNUSED 36 #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 45 #define J721E_SERDES2_LANE1_PCIE2_LANE1 37 #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 46 #define J721E_SERDES2_LANE1_USB3_1 38 #define J721E_SERDES2_LANE1_USB3_1 0x2 47 #define J721E_SERDES2_LANE1_SGMII_LANE1 39 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 48 40 49 #define J721E_SERDES3_LANE0_IP1_UNUSED 41 #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 50 #define J721E_SERDES3_LANE0_PCIE3_LANE0 42 #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 51 #define J721E_SERDES3_LANE0_USB3_0_SWAP 43 #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 52 #define J721E_SERDES3_LANE0_IP4_UNUSED 44 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 53 45 54 #define J721E_SERDES3_LANE1_IP1_UNUSED 46 #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 55 #define J721E_SERDES3_LANE1_PCIE3_LANE1 47 #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 56 #define J721E_SERDES3_LANE1_USB3_0 48 #define J721E_SERDES3_LANE1_USB3_0 0x2 57 #define J721E_SERDES3_LANE1_IP4_UNUSED 49 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 58 50 59 #define J721E_SERDES4_LANE0_EDP_LANE0 51 #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 60 #define J721E_SERDES4_LANE0_IP2_UNUSED 52 #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 61 #define J721E_SERDES4_LANE0_QSGMII_LANE5 53 #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 62 #define J721E_SERDES4_LANE0_IP4_UNUSED 54 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 63 55 64 #define J721E_SERDES4_LANE1_EDP_LANE1 56 #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 65 #define J721E_SERDES4_LANE1_IP2_UNUSED 57 #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 66 #define J721E_SERDES4_LANE1_QSGMII_LANE6 58 #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 67 #define J721E_SERDES4_LANE1_IP4_UNUSED 59 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 68 60 69 #define J721E_SERDES4_LANE2_EDP_LANE2 61 #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 70 #define J721E_SERDES4_LANE2_IP2_UNUSED 62 #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 71 #define J721E_SERDES4_LANE2_QSGMII_LANE7 63 #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 72 #define J721E_SERDES4_LANE2_IP4_UNUSED 64 #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 73 65 74 #define J721E_SERDES4_LANE3_EDP_LANE3 66 #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 75 #define J721E_SERDES4_LANE3_IP2_UNUSED 67 #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 76 #define J721E_SERDES4_LANE3_QSGMII_LANE8 68 #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 77 #define J721E_SERDES4_LANE3_IP4_UNUSED 69 #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 78 70 79 /* J7200 */ 71 /* J7200 */ 80 72 81 #define J7200_SERDES0_LANE0_QSGMII_LANE3 73 #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 82 #define J7200_SERDES0_LANE0_PCIE1_LANE0 74 #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 83 #define J7200_SERDES0_LANE0_IP3_UNUSED 75 #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 84 #define J7200_SERDES0_LANE0_IP4_UNUSED 76 #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 85 77 86 #define J7200_SERDES0_LANE1_QSGMII_LANE4 78 #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 87 #define J7200_SERDES0_LANE1_PCIE1_LANE1 79 #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 88 #define J7200_SERDES0_LANE1_IP3_UNUSED 80 #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 89 #define J7200_SERDES0_LANE1_IP4_UNUSED 81 #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 90 82 91 #define J7200_SERDES0_LANE2_QSGMII_LANE1 83 #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 92 #define J7200_SERDES0_LANE2_PCIE1_LANE2 84 #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 93 #define J7200_SERDES0_LANE2_IP3_UNUSED 85 #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 94 #define J7200_SERDES0_LANE2_IP4_UNUSED 86 #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 95 87 96 #define J7200_SERDES0_LANE3_QSGMII_LANE2 88 #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 97 #define J7200_SERDES0_LANE3_PCIE1_LANE3 89 #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 98 #define J7200_SERDES0_LANE3_USB 90 #define J7200_SERDES0_LANE3_USB 0x2 99 #define J7200_SERDES0_LANE3_IP4_UNUSED 91 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 100 92 101 /* AM64 */ 93 /* AM64 */ 102 94 103 #define AM64_SERDES0_LANE0_PCIE0 95 #define AM64_SERDES0_LANE0_PCIE0 0x0 104 #define AM64_SERDES0_LANE0_USB 96 #define AM64_SERDES0_LANE0_USB 0x1 105 97 106 /* J721S2 */ 98 /* J721S2 */ 107 99 108 #define J721S2_SERDES0_LANE0_EDP_LANE0 100 #define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 109 #define J721S2_SERDES0_LANE0_PCIE1_LANE0 101 #define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 110 #define J721S2_SERDES0_LANE0_IP3_UNUSED 102 #define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 111 #define J721S2_SERDES0_LANE0_IP4_UNUSED 103 #define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 112 104 113 #define J721S2_SERDES0_LANE1_EDP_LANE1 105 #define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 114 #define J721S2_SERDES0_LANE1_PCIE1_LANE1 106 #define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 115 #define J721S2_SERDES0_LANE1_USB 107 #define J721S2_SERDES0_LANE1_USB 0x2 116 #define J721S2_SERDES0_LANE1_IP4_UNUSED 108 #define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 117 109 118 #define J721S2_SERDES0_LANE2_EDP_LANE2 110 #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 119 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 111 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 120 #define J721S2_SERDES0_LANE2_IP3_UNUSED 112 #define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 121 #define J721S2_SERDES0_LANE2_IP4_UNUSED 113 #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 122 114 123 #define J721S2_SERDES0_LANE3_EDP_LANE3 115 #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 124 #define J721S2_SERDES0_LANE3_PCIE1_LANE3 116 #define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 125 #define J721S2_SERDES0_LANE3_USB 117 #define J721S2_SERDES0_LANE3_USB 0x2 126 #define J721S2_SERDES0_LANE3_IP4_UNUSED 118 #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 127 119 128 /* J784S4 */ 120 /* J784S4 */ 129 121 130 #define J784S4_SERDES0_LANE0_IP1_UNUSED 122 #define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 131 #define J784S4_SERDES0_LANE0_PCIE1_LANE0 123 #define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 132 #define J784S4_SERDES0_LANE0_IP3_UNUSED 124 #define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 133 #define J784S4_SERDES0_LANE0_IP4_UNUSED 125 #define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 134 126 135 #define J784S4_SERDES0_LANE1_IP1_UNUSED 127 #define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 136 #define J784S4_SERDES0_LANE1_PCIE1_LANE1 128 #define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 137 #define J784S4_SERDES0_LANE1_IP3_UNUSED 129 #define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 138 #define J784S4_SERDES0_LANE1_IP4_UNUSED 130 #define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 139 131 140 #define J784S4_SERDES0_LANE2_PCIE3_LANE0 132 #define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 141 #define J784S4_SERDES0_LANE2_PCIE1_LANE2 133 #define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 142 #define J784S4_SERDES0_LANE2_IP3_UNUSED 134 #define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 143 #define J784S4_SERDES0_LANE2_IP4_UNUSED 135 #define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 144 136 145 #define J784S4_SERDES0_LANE3_PCIE3_LANE1 137 #define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 146 #define J784S4_SERDES0_LANE3_PCIE1_LANE3 138 #define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 147 #define J784S4_SERDES0_LANE3_USB 139 #define J784S4_SERDES0_LANE3_USB 0x2 148 #define J784S4_SERDES0_LANE3_IP4_UNUSED 140 #define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 149 141 150 #define J784S4_SERDES1_LANE0_QSGMII_LANE3 142 #define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 151 #define J784S4_SERDES1_LANE0_PCIE0_LANE0 143 #define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 152 #define J784S4_SERDES1_LANE0_IP3_UNUSED 144 #define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 153 #define J784S4_SERDES1_LANE0_IP4_UNUSED 145 #define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 154 146 155 #define J784S4_SERDES1_LANE1_QSGMII_LANE4 147 #define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 156 #define J784S4_SERDES1_LANE1_PCIE0_LANE1 148 #define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 157 #define J784S4_SERDES1_LANE1_IP3_UNUSED 149 #define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 158 #define J784S4_SERDES1_LANE1_IP4_UNUSED 150 #define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 159 151 160 #define J784S4_SERDES1_LANE2_QSGMII_LANE1 152 #define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 161 #define J784S4_SERDES1_LANE2_PCIE0_LANE2 153 #define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 162 #define J784S4_SERDES1_LANE2_PCIE2_LANE0 154 #define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 163 #define J784S4_SERDES1_LANE2_IP4_UNUSED 155 #define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 164 156 165 #define J784S4_SERDES1_LANE3_QSGMII_LANE2 157 #define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 166 #define J784S4_SERDES1_LANE3_PCIE0_LANE3 158 #define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 167 #define J784S4_SERDES1_LANE3_PCIE2_LANE1 159 #define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 168 #define J784S4_SERDES1_LANE3_IP4_UNUSED 160 #define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 169 161 170 #define J784S4_SERDES2_LANE0_QSGMII_LANE5 162 #define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 171 #define J784S4_SERDES2_LANE0_IP2_UNUSED 163 #define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 172 #define J784S4_SERDES2_LANE0_IP3_UNUSED 164 #define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 173 #define J784S4_SERDES2_LANE0_IP4_UNUSED 165 #define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 174 166 175 #define J784S4_SERDES2_LANE1_QSGMII_LANE6 167 #define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 176 #define J784S4_SERDES2_LANE1_IP2_UNUSED 168 #define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 177 #define J784S4_SERDES2_LANE1_IP3_UNUSED 169 #define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 178 #define J784S4_SERDES2_LANE1_IP4_UNUSED 170 #define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 179 171 180 #define J784S4_SERDES2_LANE2_QSGMII_LANE7 172 #define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 181 #define J784S4_SERDES2_LANE2_QSGMII_LANE1 173 #define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 182 #define J784S4_SERDES2_LANE2_IP3_UNUSED 174 #define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 183 #define J784S4_SERDES2_LANE2_IP4_UNUSED 175 #define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 184 176 185 #define J784S4_SERDES2_LANE3_QSGMII_LANE8 177 #define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 186 #define J784S4_SERDES2_LANE3_QSGMII_LANE2 178 #define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 187 #define J784S4_SERDES2_LANE3_IP3_UNUSED 179 #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 188 #define J784S4_SERDES2_LANE3_IP4_UNUSED 180 #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 189 181 190 #endif /* _DT_BINDINGS_MUX_TI_SERDES */ 182 #endif /* _DT_BINDINGS_MUX_TI_SERDES */ 191 183
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.